DS_DMA
Signals | Component Instantiations | Processes
ctrl_ext_descriptor Architecture Reference
Граф наследования:ctrl_ext_descriptor:
ctrl_ext_descriptor block_pe_fifo_ext ctrl_ext_descriptor_pkg block_pe_fifo_ext block_pe_fifo_ext_pkg pcie_core64_m1 pcie_core64_m4 pcie_core64_m6 pcie_core64_m1 pcie_core64_m4 pcie_core64_m6 pcie_core64_m1_pkg pcie_core64_m2 pcie_core64_m4_pkg pcie_core64_m5 pcie_core64_m6_pkg pcie_core64_m7 pcie_core64_m2 pcie_core64_m5 pcie_core64_m7 pcie_core64_m2_pkg pcie_core64_m5_pkg pcie_core64_m7_pkg

Полный список членов класса



Processes

pr_dsp  ( clk )
pr_crc  ( clk )
pr_sig  ( clk )

Signals

ram_a_out  std_logic_vector ( 63 downto 0 )
ram_a_in  std_logic_vector ( 63 downto 0 )
ram_a_adr  std_logic_vector ( 8 downto 0 )
ram_a_wr  std_logic
ram_b_wr  std_logic
ram_b_adr  std_logic_vector ( 8 downto 0 )
reg_write  std_logic
status  std_logic_vector ( 7 downto 0 )
port_a  std_logic_vector ( 17 downto 0 )
port_b  std_logic_vector ( 17 downto 0 )
port_c  std_logic_vector ( 47 downto 0 )
port_p  std_logic_vector ( 47 downto 0 )
opmode  std_logic_vector ( 6 downto 0 )
carry  std_logic
reg_0  std_logic_vector ( 7 downto 0 )
reg_1  std_logic_vector ( 7 downto 0 )
reg_2  std_logic_vector ( 7 downto 0 )
reg0_z  std_logic
crc_reset  std_logic
crc  std_logic_vector ( 15 downto 0 )
crc_z  std_logic
sig_error  std_logic
dma_descriptor_error  std_logic

Component Instantiations

ram0  RAMB16_S36_S36
ram1  RAMB16_S36_S36
dsp  DSP48
ram_adr  ram16x1d

Подробное описание

См. определение в файле ctrl_ext_descriptor.vhd строка 150


Объявления и описания членов класса находятся в файле: