Граф наследования:ctrl_main:
Architectures | |
| ctrl_main | Architecture |
Libraries | |
| ieee | |
| unisim | |
Packages | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| vcomponents | |
Ports | |
| reset | in std_logic |
| clk | in std_logic |
| dma0_ctrl | in std_logic_vector ( 7 downto 0 ) |
| dma1_ctrl | in std_logic_vector ( 7 downto 0 ) |
| dma0_transfer_rdy | in std_logic |
| dma1_transfer_rdy | in std_logic |
| dma_chn | out std_logic |
| ram_do | out std_logic_vector ( 7 downto 0 ) |
| ram_adr | out std_logic_vector ( 8 downto 0 ) |
| ram_we | out std_logic |
| dma0_eot_clr | in std_logic |
| dma1_eot_clr | in std_logic |
| reg_dma0_status | out std_logic_vector ( 15 downto 0 ) |
| reg_dma1_status | out std_logic_vector ( 15 downto 0 ) |
| ram_change | out std_logic |
| loc_adr_we | out std_logic |
| pci_adr_we | out std_logic |
| pci_adr_h_we | out std_logic |
| dsc_correct | in std_logic |
| dsc_cmd | in std_logic_vector ( 7 downto 0 ) |
| dsc_change_adr | out std_logic |
| dsc_change_mode | out std_logic |
| dsc_load_en | out std_logic |
| dma_reg0 | out std_logic_vector ( 2 downto 0 ) |
| dma_change_adr | out std_logic |
| dma_status | in std_logic_vector ( 2 downto 0 ) |
Подробное описание
См. определение в файле ctrl_main.vhd строка 95
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_main.vhd
