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DS_DMA
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Architectures | |
| ctrl_ram_cmd | Architecture |
Libraries | |
| ieee | |
| unisim | |
Packages | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| vcomponents | |
| ctrl_ram_cmd_pb_pkg | Package <ctrl_ram_cmd_pb_pkg> |
Generics | |
| is_dsp48 | in integer := 1 |
Ports | |
| reset | in std_logic |
| clk | in std_logic |
| Тактовая частота ядра - 250 МГц | |
| aclk | in std_logic |
| Тактовая частота локальной шины - 266 МГц | |
| dma_chn | in std_logic |
| reg_ch0_ctrl | in std_logic_vector ( 7 downto 0 ) |
| reg_ch1_ctrl | in std_logic_vector ( 7 downto 0 ) |
| reg_write_E0 | in std_logic |
| dma0_transfer_rdy | out std_logic |
| dma1_transfer_rdy | out std_logic |
| dmar0 | in std_logic |
| dmar1 | in std_logic |
| request_wr | out std_logic |
| 1 - запрос на запись в регистр | |
| request_rd | out std_logic |
| 1 - запрос на чтение из регистра | |
| allow_wr | in std_logic |
| 1 - разрешение записи | |
| pf_repack_we | in std_logic |
| pf_ram_rd_out | out std_logic |
| ram_adra_a9 | out std_logic |
| ram_adrb | out std_logic_vector ( 10 downto 0 ) |
См. определение в файле ctrl_ram_cmd.vhd строка 83
1.7.4