|
DS_DMA
|
Architectures | |
| v6_pcie | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| std_logic_unsigned | |
Generics | |
| UPSTREAM_FACING | boolean := true |
| PL_FAST_TRAIN | boolean := false |
| LINK_CAP_MAX_LINK_WIDTH | bit_vector := x " 08 " |
Ports | |
| pipe_clk | in std_logic |
| pl_phy_lnkup_n | in std_logic |
| pl_ltssm_state | in std_logic_vector ( 5 downto 0 ) |
| pl_sel_lnk_rate | in std_logic |
| pl_directed_link_change | in std_logic_vector ( 1 downto 0 ) |
| cfg_link_status_negotiated_width | in std_logic_vector ( 3 downto 0 ) |
| pipe_rx0_data | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx0_char_isk | in std_logic_vector ( 1 downto 0 ) |
| filter_pipe | out std_logic |
См. определение в файле pcie_upconfig_fix_3451_v6.vhd строка 62
1.7.4