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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Spartan-6 Integrated Block for PCI Express 00051 -- File : cl_s6pcie_m2.vhd 00052 -- Description: Spartan-6 solution wrapper : Endpoint for PCI Express 00053 -- 00054 ------------------------------------------------------------------------------- 00055 00056 library ieee; 00057 use ieee.std_logic_1164.all; 00058 use ieee.std_logic_arith.all; 00059 use ieee.std_logic_unsigned.all; 00060 use ieee.numeric_bit.all; 00061 library unisim; 00062 use unisim.vcomponents.all; 00063 --synthesis translate_off 00064 use unisim.vpkg.all; 00065 library secureip; 00066 use secureip.all; 00067 --synthesis translate_on 00068 00069 entity cl_s6pcie_m2 is 00070 generic ( 00071 TL_TX_RAM_RADDR_LATENCY : integer := 0; 00072 TL_TX_RAM_RDATA_LATENCY : integer := 2; 00073 TL_RX_RAM_RADDR_LATENCY : integer := 0; 00074 TL_RX_RAM_RDATA_LATENCY : integer := 2; 00075 TL_RX_RAM_WRITE_LATENCY : integer := 0; 00076 VC0_TX_LASTPACKET : integer := 28; 00077 VC0_RX_RAM_LIMIT : bit_vector := x"7FF"; 00078 VC0_TOTAL_CREDITS_PH : integer := 32; 00079 VC0_TOTAL_CREDITS_PD : integer := 211; 00080 VC0_TOTAL_CREDITS_NPH : integer := 8; 00081 VC0_TOTAL_CREDITS_CH : integer := 40; 00082 VC0_TOTAL_CREDITS_CD : integer := 211; 00083 VC0_CPL_INFINITE : boolean := TRUE; 00084 BAR0 : bit_vector := x"FFE00000"; 00085 BAR1 : bit_vector := x"FFE00000"; 00086 BAR2 : bit_vector := x"00000000"; 00087 BAR3 : bit_vector := x"00000000"; 00088 BAR4 : bit_vector := x"00000000"; 00089 BAR5 : bit_vector := x"00000000"; 00090 EXPANSION_ROM : bit_vector := "0000000000000000000000"; 00091 DISABLE_BAR_FILTERING : boolean := FALSE; 00092 DISABLE_ID_CHECK : boolean := FALSE; 00093 TL_TFC_DISABLE : boolean := FALSE; 00094 TL_TX_CHECKS_DISABLE : boolean := FALSE; 00095 USR_CFG : boolean := FALSE; 00096 USR_EXT_CFG : boolean := FALSE; 00097 DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 1; 00098 CLASS_CODE : bit_vector := x"FFFFFF"; 00099 CARDBUS_CIS_POINTER : bit_vector := x"00000000"; 00100 PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1"; 00101 PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"0"; 00102 PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; 00103 PCIE_CAP_INT_MSG_NUM : bit_vector := "00000"; 00104 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; 00105 DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; 00106 DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7; 00107 DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; 00108 SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; 00109 SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; 00110 SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; 00111 DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; 00112 LINK_CAP_ASPM_SUPPORT : integer := 1; 00113 LINK_CAP_L0S_EXIT_LATENCY : integer := 7; 00114 LINK_CAP_L1_EXIT_LATENCY : integer := 7; 00115 LL_ACK_TIMEOUT : bit_vector := x"0000"; 00116 LL_ACK_TIMEOUT_EN : boolean := FALSE; 00117 LL_REPLAY_TIMEOUT : bit_vector := x"0000"; 00118 LL_REPLAY_TIMEOUT_EN : boolean := FALSE; 00119 MSI_CAP_MULTIMSGCAP : integer := 0; 00120 MSI_CAP_MULTIMSG_EXTENSION : integer := 0; 00121 LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE; 00122 PLM_AUTO_CONFIG : boolean := FALSE; 00123 FAST_TRAIN : boolean := FALSE; 00124 ENABLE_RX_TD_ECRC_TRIM : boolean := TRUE; 00125 DISABLE_SCRAMBLING : boolean := FALSE; 00126 PM_CAP_VERSION : integer := 3; 00127 PM_CAP_PME_CLOCK : boolean := FALSE; 00128 PM_CAP_DSI : boolean := FALSE; 00129 PM_CAP_AUXCURRENT : integer := 0; 00130 PM_CAP_D1SUPPORT : boolean := TRUE; 00131 PM_CAP_D2SUPPORT : boolean := TRUE; 00132 PM_CAP_PMESUPPORT : bit_vector := x"0F"; 00133 PM_DATA0 : bit_vector := x"00"; 00134 PM_DATA_SCALE0 : bit_vector := x"0"; 00135 PM_DATA1 : bit_vector := x"00"; 00136 PM_DATA_SCALE1 : bit_vector := x"0"; 00137 PM_DATA2 : bit_vector := x"00"; 00138 PM_DATA_SCALE2 : bit_vector := x"0"; 00139 PM_DATA3 : bit_vector := x"00"; 00140 PM_DATA_SCALE3 : bit_vector := x"0"; 00141 PM_DATA4 : bit_vector := x"00"; 00142 PM_DATA_SCALE4 : bit_vector := x"0"; 00143 PM_DATA5 : bit_vector := x"00"; 00144 PM_DATA_SCALE5 : bit_vector := x"0"; 00145 PM_DATA6 : bit_vector := x"00"; 00146 PM_DATA_SCALE6 : bit_vector := x"0"; 00147 PM_DATA7 : bit_vector := x"00"; 00148 PM_DATA_SCALE7 : bit_vector := x"0"; 00149 PCIE_GENERIC : bit_vector := "000010101111"; 00150 GTP_SEL : integer := 0; 00151 CFG_VEN_ID : std_logic_vector(15 downto 0) := x"4953"; 00152 CFG_DEV_ID : std_logic_vector(15 downto 0) := x"5507"; 00153 CFG_REV_ID : std_logic_vector(7 downto 0) := x"10"; 00154 CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"4953"; 00155 CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"0008"; 00156 REF_CLK_FREQ : integer := 1 00157 ); 00158 port ( 00159 -- PCI Express Fabric Interface 00160 pci_exp_txp : out std_logic; 00161 pci_exp_txn : out std_logic; 00162 pci_exp_rxp : in std_logic; 00163 pci_exp_rxn : in std_logic; 00164 00165 -- Transaction (TRN) Interface 00166 trn_lnk_up_n : out std_logic; 00167 00168 -- Tx 00169 trn_td : in std_logic_vector(31 downto 0); 00170 trn_tsof_n : in std_logic; 00171 trn_teof_n : in std_logic; 00172 trn_tsrc_rdy_n : in std_logic; 00173 trn_tdst_rdy_n : out std_logic; 00174 trn_terr_drop_n : out std_logic; 00175 trn_tsrc_dsc_n : in std_logic; 00176 trn_terrfwd_n : in std_logic; 00177 trn_tbuf_av : out std_logic_vector(5 downto 0); 00178 trn_tstr_n : in std_logic; 00179 trn_tcfg_req_n : out std_logic; 00180 trn_tcfg_gnt_n : in std_logic; 00181 00182 -- Rx 00183 trn_rd : out std_logic_vector(31 downto 0); 00184 trn_rsof_n : out std_logic; 00185 trn_reof_n : out std_logic; 00186 trn_rsrc_rdy_n : out std_logic; 00187 trn_rsrc_dsc_n : out std_logic; 00188 trn_rdst_rdy_n : in std_logic; 00189 trn_rerrfwd_n : out std_logic; 00190 trn_rnp_ok_n : in std_logic; 00191 trn_rbar_hit_n : out std_logic_vector(6 downto 0); 00192 trn_fc_sel : in std_logic_vector(2 downto 0); 00193 trn_fc_nph : out std_logic_vector(7 downto 0); 00194 trn_fc_npd : out std_logic_vector(11 downto 0); 00195 trn_fc_ph : out std_logic_vector(7 downto 0); 00196 trn_fc_pd : out std_logic_vector(11 downto 0); 00197 trn_fc_cplh : out std_logic_vector(7 downto 0); 00198 trn_fc_cpld : out std_logic_vector(11 downto 0); 00199 00200 -- Host (CFG) Interface 00201 cfg_do : out std_logic_vector(31 downto 0); 00202 cfg_rd_wr_done_n : out std_logic; 00203 cfg_dwaddr : in std_logic_vector(9 downto 0); 00204 cfg_rd_en_n : in std_logic; 00205 cfg_err_ur_n : in std_logic; 00206 cfg_err_cor_n : in std_logic; 00207 cfg_err_ecrc_n : in std_logic; 00208 cfg_err_cpl_timeout_n : in std_logic; 00209 cfg_err_cpl_abort_n : in std_logic; 00210 cfg_err_posted_n : in std_logic; 00211 cfg_err_locked_n : in std_logic; 00212 cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0); 00213 cfg_err_cpl_rdy_n : out std_logic; 00214 cfg_interrupt_n : in std_logic; 00215 cfg_interrupt_rdy_n : out std_logic; 00216 cfg_interrupt_assert_n : in std_logic; 00217 cfg_interrupt_do : out std_logic_vector(7 downto 0); 00218 cfg_interrupt_di : in std_logic_vector(7 downto 0); 00219 cfg_interrupt_mmenable : out std_logic_vector(2 downto 0); 00220 cfg_interrupt_msienable : out std_logic; 00221 cfg_turnoff_ok_n : in std_logic; 00222 cfg_to_turnoff_n : out std_logic; 00223 cfg_pm_wake_n : in std_logic; 00224 cfg_pcie_link_state_n : out std_logic_vector(2 downto 0); 00225 cfg_trn_pending_n : in std_logic; 00226 cfg_dsn : in std_logic_vector(63 downto 0); 00227 cfg_bus_number : out std_logic_vector(7 downto 0); 00228 cfg_device_number : out std_logic_vector(4 downto 0); 00229 cfg_function_number : out std_logic_vector(2 downto 0); 00230 cfg_status : out std_logic_vector(15 downto 0); 00231 cfg_command : out std_logic_vector(15 downto 0); 00232 cfg_dstatus : out std_logic_vector(15 downto 0); 00233 cfg_dcommand : out std_logic_vector(15 downto 0); 00234 cfg_lstatus : out std_logic_vector(15 downto 0); 00235 cfg_lcommand : out std_logic_vector(15 downto 0); 00236 00237 -- System Interface 00238 sys_clk : in std_logic; 00239 sys_reset_n : in std_logic; 00240 trn_clk : out std_logic; 00241 trn_reset_n : out std_logic; 00242 received_hot_reset : out std_logic 00243 ); 00244 end cl_s6pcie_m2; 00245 00246 architecture rtl of cl_s6pcie_m2 is 00247 00248 attribute CORE_GENERATION_INFO : STRING; 00249 attribute CORE_GENERATION_INFO of rtl : architecture is 00250 "cl_s6pcie_m2,s6_pcie_v1_4,{TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=211,VC0_TOTAL_CREDITS_NPH=8,VC0_TOTAL_CREDITS_CH=40,VC0_TOTAL_CREDITS_CD=211,VC0_CPL_INFINITE=TRUE,BAR0=FFE00000,BAR1=FFE00000,BAR2=00000000,BAR3=00000000,BAR4=00000000,BAR5=00000000,EXPANSION_ROM=000000,USR_CFG=FALSE,USR_EXT_CFG=FALSE,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,CLASS_CODE=FFFFFF,CARDBUS_CIS_POINTER=00000000,PCIE_CAP_CAPABILITY_VERSION=1,PCIE_CAP_DEVICE_PORT_TYPE=0,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,DEV_CAP_ENDPOINT_L0S_LATENCY=7,DEV_CAP_ENDPOINT_L1_LATENCY=7,LINK_CAP_ASPM_SUPPORT=1,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_SCRAMBLING=FALSE,PM_CAP_DSI=FALSE,PM_CAP_D1SUPPORT=TRUE,PM_CAP_D2SUPPORT=TRUE,PM_CAP_PMESUPPORT=0F,PM_DATA0=00,PM_DATA_SCALE0=0,PM_DATA1=00,PM_DATA_SCALE1=0,PM_DATA2=00,PM_DATA_SCALE2=0,PM_DATA3=00,PM_DATA_SCALE3=0,PM_DATA4=00,PM_DATA_SCALE4=0,PM_DATA5=00,PM_DATA_SCALE5=0,PM_DATA6=00,PM_DATA_SCALE6=0,PM_DATA7=00,PM_DATA_SCALE7=0,PCIE_GENERIC=000010101111,GTP_SEL=0,CFG_VEN_ID=4953,CFG_DEV_ID=5507,CFG_REV_ID=10,CFG_SUBSYS_VEN_ID=4953,CFG_SUBSYS_ID=0008,REF_CLK_FREQ=1}"; 00251 00252 ------------------------ 00253 -- Function Declarations 00254 ------------------------ 00255 function CALC_CLKFBOUT_MULT(FREQ_SEL : integer) return integer is 00256 begin 00257 case FREQ_SEL is 00258 when 0 => return 5; -- 100 MHz 00259 when others => return 4; -- 125 MHz 00260 end case; 00261 end CALC_CLKFBOUT_MULT; 00262 function CALC_CLKIN_PERIOD(FREQ_SEL : integer) return real is 00263 begin 00264 case FREQ_SEL is 00265 when 0 => return 10.0; -- 100 MHz 00266 when others => return 8.0; -- 125 MHz 00267 end case; 00268 end CALC_CLKIN_PERIOD; 00269 function CALC_CLK25_DIVIDER(FREQ_SEL : integer) return integer is 00270 begin 00271 case FREQ_SEL is 00272 when 0 => return 4; -- 100 MHz 00273 when others => return 5; -- 125 MHz 00274 end case; 00275 end CALC_CLK25_DIVIDER; 00276 function CALC_PLL_DIVSEL_FB(FREQ_SEL : integer) return integer is 00277 begin 00278 case FREQ_SEL is 00279 when 0 => return 5; -- 100 MHz 00280 when others => return 2; -- 125 MHz 00281 end case; 00282 end CALC_PLL_DIVSEL_FB; 00283 function CALC_PLL_DIVSEL_REF(FREQ_SEL : integer) return integer is 00284 begin 00285 case FREQ_SEL is 00286 when 0 => return 2; -- 100 MHz 00287 when others => return 1; -- 125 MHz 00288 end case; 00289 end CALC_PLL_DIVSEL_REF; 00290 function SIM_INT(SIMULATION : boolean) return integer is 00291 begin 00292 if SIMULATION then 00293 return 1; 00294 else 00295 return 0; 00296 end if; 00297 end SIM_INT; 00298 00299 ------------------------ 00300 -- Constant Declarations 00301 ------------------------ 00302 00303 constant CLKFBOUT_MULT : integer := CALC_CLKFBOUT_MULT(REF_CLK_FREQ); 00304 constant CLKIN_PERIOD : real := CALC_CLKIN_PERIOD(REF_CLK_FREQ); 00305 constant GT_CLK25_DIVIDER : integer := CALC_CLK25_DIVIDER(REF_CLK_FREQ); 00306 constant GT_PLL_DIVSEL_FB : integer := CALC_PLL_DIVSEL_FB(REF_CLK_FREQ); 00307 constant GT_PLL_DIVSEL_REF : integer := CALC_PLL_DIVSEL_REF(REF_CLK_FREQ); 00308 00309 ------------------------- 00310 -- Component Declarations 00311 ------------------------- 00312 component pcie_bram_top_s6 is 00313 generic ( 00314 DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 0; 00315 00316 VC0_TX_LASTPACKET : integer := 31; 00317 TLM_TX_OVERHEAD : integer := 24; 00318 TL_TX_RAM_RADDR_LATENCY : integer := 1; 00319 TL_TX_RAM_RDATA_LATENCY : integer := 1; 00320 TL_TX_RAM_WRITE_LATENCY : integer := 1; 00321 00322 VC0_RX_LIMIT : integer := 16#1FFF#; 00323 TL_RX_RAM_RADDR_LATENCY : integer := 1; 00324 TL_RX_RAM_RDATA_LATENCY : integer := 1; 00325 TL_RX_RAM_WRITE_LATENCY : integer := 1 00326 ); 00327 port ( 00328 user_clk_i : in std_logic; 00329 reset_i : in std_logic; 00330 00331 mim_tx_wen : in std_logic; 00332 mim_tx_waddr : in std_logic_vector(11 downto 0); 00333 mim_tx_wdata : in std_logic_vector(35 downto 0); 00334 mim_tx_ren : in std_logic; 00335 mim_tx_rce : in std_logic; 00336 mim_tx_raddr : in std_logic_vector(11 downto 0); 00337 mim_tx_rdata : out std_logic_vector(35 downto 0); 00338 00339 mim_rx_wen : in std_logic; 00340 mim_rx_waddr : in std_logic_vector(11 downto 0); 00341 mim_rx_wdata : in std_logic_vector(35 downto 0); 00342 mim_rx_ren : in std_logic; 00343 mim_rx_rce : in std_logic; 00344 mim_rx_raddr : in std_logic_vector(11 downto 0); 00345 mim_rx_rdata : out std_logic_vector(35 downto 0) 00346 ); 00347 end component pcie_bram_top_s6; 00348 00349 component GTPA1_DUAL_WRAPPER is 00350 generic 00351 ( 00352 -- Simulation attributes 00353 WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset 00354 WRAPPER_CLK25_DIVIDER_0 : integer := 4; 00355 WRAPPER_CLK25_DIVIDER_1 : integer := 4; 00356 WRAPPER_PLL_DIVSEL_FB_0 : integer := 5; 00357 WRAPPER_PLL_DIVSEL_FB_1 : integer := 5; 00358 WRAPPER_PLL_DIVSEL_REF_0 : integer := 2; 00359 WRAPPER_PLL_DIVSEL_REF_1 : integer := 2; 00360 WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation 00361 ); 00362 port 00363 ( 00364 00365 --_________________________________________________________________________ 00366 --_________________________________________________________________________ 00367 --TILE0 (X0_Y0) 00368 00369 ------------------------ Loopback and Powerdown Ports ---------------------- 00370 TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00371 TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00372 TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0); 00373 TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0); 00374 --------------------------------- PLL Ports -------------------------------- 00375 TILE0_CLK00_IN : in std_logic; 00376 TILE0_CLK01_IN : in std_logic; 00377 TILE0_GTPRESET0_IN : in std_logic; 00378 TILE0_GTPRESET1_IN : in std_logic; 00379 TILE0_PLLLKDET0_OUT : out std_logic; 00380 TILE0_PLLLKDET1_OUT : out std_logic; 00381 TILE0_RESETDONE0_OUT : out std_logic; 00382 TILE0_RESETDONE1_OUT : out std_logic; 00383 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00384 TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0); 00385 TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0); 00386 TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0); 00387 TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0); 00388 TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0); 00389 TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0); 00390 ---------------------- Receive Ports - Clock Correction -------------------- 00391 TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0); 00392 TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0); 00393 --------------- Receive Ports - Comma Detection and Alignment -------------- 00394 TILE0_RXENMCOMMAALIGN0_IN : in std_logic; 00395 TILE0_RXENMCOMMAALIGN1_IN : in std_logic; 00396 TILE0_RXENPCOMMAALIGN0_IN : in std_logic; 00397 TILE0_RXENPCOMMAALIGN1_IN : in std_logic; 00398 ------------------- Receive Ports - RX Data Path interface ----------------- 00399 TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0); 00400 TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0); 00401 TILE0_RXRESET0_IN : in std_logic; 00402 TILE0_RXRESET1_IN : in std_logic; 00403 TILE0_RXUSRCLK0_IN : in std_logic; 00404 TILE0_RXUSRCLK1_IN : in std_logic; 00405 TILE0_RXUSRCLK20_IN : in std_logic; 00406 TILE0_RXUSRCLK21_IN : in std_logic; 00407 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00408 TILE0_GATERXELECIDLE0_IN : in std_logic; 00409 TILE0_GATERXELECIDLE1_IN : in std_logic; 00410 TILE0_IGNORESIGDET0_IN : in std_logic; 00411 TILE0_IGNORESIGDET1_IN : in std_logic; 00412 TILE0_RXELECIDLE0_OUT : out std_logic; 00413 TILE0_RXELECIDLE1_OUT : out std_logic; 00414 TILE0_RXN0_IN : in std_logic; 00415 TILE0_RXN1_IN : in std_logic; 00416 TILE0_RXP0_IN : in std_logic; 00417 TILE0_RXP1_IN : in std_logic; 00418 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00419 TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0); 00420 TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0); 00421 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00422 TILE0_PHYSTATUS0_OUT : out std_logic; 00423 TILE0_PHYSTATUS1_OUT : out std_logic; 00424 TILE0_RXVALID0_OUT : out std_logic; 00425 TILE0_RXVALID1_OUT : out std_logic; 00426 -------------------- Receive Ports - RX Polarity Control ------------------- 00427 TILE0_RXPOLARITY0_IN : in std_logic; 00428 TILE0_RXPOLARITY1_IN : in std_logic; 00429 ---------------------------- TX/RX Datapath Ports -------------------------- 00430 TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0); 00431 TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0); 00432 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00433 TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0); 00434 TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0); 00435 TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0); 00436 TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0); 00437 ------------------ Transmit Ports - TX Data Path interface ----------------- 00438 TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0); 00439 TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0); 00440 TILE0_TXUSRCLK0_IN : in std_logic; 00441 TILE0_TXUSRCLK1_IN : in std_logic; 00442 TILE0_TXUSRCLK20_IN : in std_logic; 00443 TILE0_TXUSRCLK21_IN : in std_logic; 00444 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00445 TILE0_TXN0_OUT : out std_logic; 00446 TILE0_TXN1_OUT : out std_logic; 00447 TILE0_TXP0_OUT : out std_logic; 00448 TILE0_TXP1_OUT : out std_logic; 00449 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00450 TILE0_TXDETECTRX0_IN : in std_logic; 00451 TILE0_TXDETECTRX1_IN : in std_logic; 00452 TILE0_TXELECIDLE0_IN : in std_logic; 00453 TILE0_TXELECIDLE1_IN : in std_logic 00454 ); 00455 end component GTPA1_DUAL_WRAPPER; 00456 00457 ---------------------- 00458 -- Signal Declarations 00459 ---------------------- 00460 00461 -- PLL Signals 00462 signal mgt_clk : std_logic; 00463 signal mgt_clk_2x : std_logic; 00464 signal clock_locked : std_logic; 00465 signal gt_refclk_out : std_logic_vector(1 downto 0); 00466 signal gt_clk_fb_west_out : std_logic; 00467 signal pll_rst : std_logic; 00468 signal clk_125 : std_logic; 00469 signal clk_250 : std_logic; 00470 signal clk_62_5 : std_logic; 00471 signal gt_refclk_buf : std_logic; 00472 signal gt_refclk_fb : std_logic; 00473 00474 signal w_cfg_ven_id : std_logic_vector(15 downto 0); 00475 signal w_cfg_dev_id : std_logic_vector(15 downto 0); 00476 signal w_cfg_rev_id : std_logic_vector(7 downto 0); 00477 signal w_cfg_subsys_ven_id : std_logic_vector(15 downto 0); 00478 signal w_cfg_subsys_id : std_logic_vector(15 downto 0); 00479 00480 signal cfg_ltssm_state : std_logic_vector(4 downto 0); 00481 signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0); 00482 signal cfg_link_control_rcb : std_logic; 00483 signal cfg_link_control_common_clock : std_logic; 00484 signal cfg_link_control_extended_sync : std_logic; 00485 signal cfg_command_interrupt_disable : std_logic; 00486 signal cfg_command_serr_en : std_logic; 00487 signal cfg_command_bus_master_enable : std_logic; 00488 signal cfg_command_mem_enable : std_logic; 00489 signal cfg_command_io_enable : std_logic; 00490 signal cfg_dev_status_ur_detected : std_logic; 00491 signal cfg_dev_status_fatal_err_detected : std_logic; 00492 signal cfg_dev_status_nonfatal_err_detected : std_logic; 00493 signal cfg_dev_status_corr_err_detected : std_logic; 00494 signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0); 00495 signal cfg_dev_control_no_snoop_en : std_logic; 00496 signal cfg_dev_control_aux_power_en : std_logic; 00497 signal cfg_dev_control_phantom_en : std_logic; 00498 signal cfg_dev_cntrol_ext_tag_en : std_logic; 00499 signal cfg_dev_control_max_payload : std_logic_vector(2 downto 0); 00500 signal cfg_dev_control_enable_ro : std_logic; 00501 signal cfg_dev_control_ext_tag_en : std_logic; 00502 signal cfg_dev_control_ur_err_reporting_en : std_logic; 00503 signal cfg_dev_control_fatal_err_reporting_en : std_logic; 00504 signal cfg_dev_control_non_fatal_reporting_en : std_logic; 00505 signal cfg_dev_control_corr_err_reporting_en : std_logic; 00506 00507 signal mim_tx_waddr : std_logic_vector(11 downto 0); 00508 signal mim_tx_raddr : std_logic_vector(11 downto 0); 00509 signal mim_rx_waddr : std_logic_vector(11 downto 0); 00510 signal mim_rx_raddr : std_logic_vector(11 downto 0); 00511 signal mim_tx_wdata : std_logic_vector(35 downto 0); 00512 signal mim_tx_rdata : std_logic_vector(35 downto 0); 00513 signal mim_rx_wdata : std_logic_vector(34 downto 0); 00514 signal mim_rx_rdata_unused : std_logic; 00515 signal mim_rx_rdata : std_logic_vector(34 downto 0); 00516 signal mim_tx_wen : std_logic; 00517 signal mim_tx_ren : std_logic; 00518 signal mim_rx_wen : std_logic; 00519 signal mim_rx_ren : std_logic; 00520 00521 signal dbg_bad_dllp_status : std_logic; 00522 signal dbg_bad_tlp_lcrc : std_logic; 00523 signal dbg_bad_tlp_seq_num : std_logic; 00524 signal dbg_bad_tlp_status : std_logic; 00525 signal dbg_dl_protocol_status : std_logic; 00526 signal dbg_fc_protocol_err_status : std_logic; 00527 signal dbg_mlfrmd_length : std_logic; 00528 signal dbg_mlfrmd_mps : std_logic; 00529 signal dbg_mlfrmd_tcvc : std_logic; 00530 signal dbg_mlfrmd_tlp_status : std_logic; 00531 signal dbg_mlfrmd_unrec_type : std_logic; 00532 signal dbg_poistlpstatus : std_logic; 00533 signal dbg_rcvr_overflow_status : std_logic; 00534 signal dbg_reg_detected_correctable : std_logic; 00535 signal dbg_reg_detected_fatal : std_logic; 00536 signal dbg_reg_detected_non_fatal : std_logic; 00537 signal dbg_reg_detected_unsupported : std_logic; 00538 signal dbg_rply_rollover_status : std_logic; 00539 signal dbg_rply_timeout_status : std_logic; 00540 signal dbg_ur_no_bar_hit : std_logic; 00541 signal dbg_ur_pois_cfg_wr : std_logic; 00542 signal dbg_ur_status : std_logic; 00543 signal dbg_ur_unsup_msg : std_logic; 00544 00545 signal pipe_gt_power_down_a : std_logic_vector(1 downto 0); 00546 signal pipe_gt_power_down_b : std_logic_vector(1 downto 0); 00547 signal pipe_gt_reset_done_a : std_logic; 00548 signal pipe_gt_reset_done_b : std_logic; 00549 signal pipe_gt_tx_elec_idle_a : std_logic; 00550 signal pipe_gt_tx_elec_idle_b : std_logic; 00551 signal pipe_phy_status_a : std_logic; 00552 signal pipe_phy_status_b : std_logic; 00553 signal pipe_rx_charisk_a : std_logic_vector(1 downto 0); 00554 signal pipe_rx_charisk_b : std_logic_vector(1 downto 0); 00555 signal pipe_rx_data_a : std_logic_vector(15 downto 0); 00556 signal pipe_rx_data_b : std_logic_vector(15 downto 0); 00557 signal pipe_rx_enter_elec_idle_a : std_logic; 00558 signal pipe_rx_enter_elec_idle_b : std_logic; 00559 signal pipe_rx_polarity_a : std_logic; 00560 signal pipe_rx_polarity_b : std_logic; 00561 signal pipe_rxreset_a : std_logic; 00562 signal pipe_rxreset_b : std_logic; 00563 signal pipe_rx_status_a : std_logic_vector(2 downto 0); 00564 signal pipe_rx_status_b : std_logic_vector(2 downto 0); 00565 signal pipe_tx_char_disp_mode_a : std_logic_vector(1 downto 0); 00566 signal pipe_tx_char_disp_mode_b : std_logic_vector(1 downto 0); 00567 signal pipe_tx_char_disp_val_a : std_logic_vector(1 downto 0); 00568 signal pipe_tx_char_disp_val_b : std_logic_vector(1 downto 0); 00569 signal pipe_tx_char_is_k_a : std_logic_vector(1 downto 0); 00570 signal pipe_tx_char_is_k_b : std_logic_vector(1 downto 0); 00571 signal pipe_tx_data_a : std_logic_vector(15 downto 0); 00572 signal pipe_tx_data_b : std_logic_vector(15 downto 0); 00573 signal pipe_tx_rcvr_det_a : std_logic; 00574 signal pipe_tx_rcvr_det_b : std_logic; 00575 00576 -- GT->PLM PIPE Interface rx 00577 signal rx_char_is_k : std_logic_vector(1 downto 0); 00578 signal rx_data : std_logic_vector(15 downto 0); 00579 signal rx_enter_elecidle : std_logic; 00580 signal rx_status : std_logic_vector(2 downto 0); 00581 signal rx_polarity : std_logic; 00582 00583 -- GT<-PLM PIPE Interface tx 00584 signal tx_char_disp_mode : std_logic_vector(1 downto 0); 00585 signal tx_char_is_k : std_logic_vector(1 downto 0); 00586 signal tx_rcvr_det : std_logic; 00587 signal tx_data : std_logic_vector(15 downto 0); 00588 00589 -- GT<->PLM PIPE Interface Misc 00590 signal phystatus : std_logic; 00591 00592 -- GT<->PLM PIPE Interface MGT Logic I/O 00593 signal gt_reset_done : std_logic; 00594 signal gt_rx_valid : std_logic; 00595 signal gt_tx_elec_idle : std_logic; 00596 signal gt_power_down : std_logic_vector(1 downto 0); 00597 signal rxreset : std_logic; 00598 signal gt_plllkdet_out : std_logic; 00599 signal sys_reset : std_logic; 00600 00601 -- Core outputs which are also used in this module - must make local copies 00602 signal trn_clk_c : std_logic; 00603 signal trn_reset_n_c : std_logic; 00604 signal trn_reset : std_logic; 00605 00606 begin 00607 00608 -- These values may be brought out and driven dynamically 00609 -- from pins rather than attributes if desired. Note - 00610 -- if they are not statically driven, the values must be 00611 -- stable before sys_reset_n is released 00612 w_cfg_ven_id <= CFG_VEN_ID; 00613 w_cfg_dev_id <= CFG_DEV_ID; 00614 w_cfg_rev_id <= CFG_REV_ID; 00615 w_cfg_subsys_ven_id <= CFG_SUBSYS_VEN_ID; 00616 w_cfg_subsys_id <= CFG_SUBSYS_ID; 00617 00618 -- Assign outputs from internal copies 00619 trn_clk <= trn_clk_c; 00620 trn_reset_n <= trn_reset_n_c; 00621 trn_reset <= not trn_reset_n_c; 00622 00623 -- Buffer reference clock from MGT 00624 gt_refclk_bufio2 : BUFIO2 00625 port map ( 00626 DIVCLK => gt_refclk_buf, 00627 IOCLK => OPEN, 00628 SERDESSTROBE => OPEN, 00629 I => gt_refclk_out(0) 00630 ); 00631 00632 pll_base_i : PLL_BASE 00633 generic map ( 00634 CLKFBOUT_MULT => CLKFBOUT_MULT, 00635 CLKFBOUT_PHASE => 0.0, 00636 CLKIN_PERIOD => CLKIN_PERIOD, 00637 CLKOUT0_DIVIDE => 2, 00638 CLKOUT0_PHASE => 0.0 , 00639 CLKOUT1_DIVIDE => 4, 00640 CLKOUT1_PHASE => 0.0 , 00641 CLKOUT2_DIVIDE => 8, 00642 CLKOUT2_PHASE => 0.0 , 00643 COMPENSATION => "INTERNAL" 00644 ) 00645 port map ( 00646 CLKIN => gt_refclk_buf, 00647 CLKFBIN => gt_refclk_fb, 00648 RST => pll_rst , 00649 CLKOUT0 => clk_250, 00650 CLKOUT1 => clk_125, 00651 CLKOUT2 => clk_62_5, 00652 CLKOUT3 => OPEN, 00653 CLKOUT4 => OPEN, 00654 CLKOUT5 => OPEN, 00655 CLKFBOUT => gt_refclk_fb, 00656 LOCKED => clock_locked 00657 ); 00658 00659 ------------------------------------- 00660 -- Instantiate buffers where required 00661 ------------------------------------- 00662 mgt_bufg : BUFG port map (O => mgt_clk, I => clk_125); 00663 mgt2x_bufg : BUFG port map (O => mgt_clk_2x, I => clk_250); 00664 phy_bufg : BUFG port map (O => trn_clk_c, I => clk_62_5 ); 00665 00666 ---------------------------- 00667 -- PCI Express BRAM Instance 00668 ---------------------------- 00669 pcie_bram_top: pcie_bram_top_s6 00670 generic map ( 00671 DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED, 00672 00673 VC0_TX_LASTPACKET => VC0_TX_LASTPACKET, 00674 TLM_TX_OVERHEAD => 20, 00675 TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY, 00676 TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY, 00677 -- NOTE: use the RX value here since there is no separate TX value 00678 TL_TX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY, 00679 00680 VC0_RX_LIMIT => conv_integer(to_stdlogicvector(VC0_RX_RAM_LIMIT)), 00681 TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY, 00682 TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY, 00683 TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY 00684 ) 00685 port map ( 00686 user_clk_i => trn_clk_c, 00687 reset_i => trn_reset, 00688 00689 mim_tx_waddr => mim_tx_waddr, 00690 mim_tx_wen => mim_tx_wen, 00691 mim_tx_ren => mim_tx_ren, 00692 mim_tx_rce => '1', 00693 mim_tx_wdata => mim_tx_wdata, 00694 mim_tx_raddr => mim_tx_raddr, 00695 mim_tx_rdata => mim_tx_rdata, 00696 00697 mim_rx_waddr => mim_rx_waddr, 00698 mim_rx_wen => mim_rx_wen, 00699 mim_rx_ren => mim_rx_ren, 00700 mim_rx_rce => '1', 00701 mim_rx_wdata(35) => '0', 00702 mim_rx_wdata(34 downto 0) => mim_rx_wdata , 00703 mim_rx_raddr => mim_rx_raddr , 00704 mim_rx_rdata(35) => mim_rx_rdata_unused, 00705 mim_rx_rdata(34 downto 0) => mim_rx_rdata 00706 ); 00707 00708 --------------------------------- 00709 -- PCI Express GTA1_DUAL Instance 00710 --------------------------------- 00711 sys_reset <= not sys_reset_n; 00712 GT_i : GTPA1_DUAL_WRAPPER 00713 generic map ( 00714 -- Simulation attributes 00715 WRAPPER_SIM_GTPRESET_SPEEDUP => 1, 00716 WRAPPER_CLK25_DIVIDER_0 => GT_CLK25_DIVIDER, 00717 WRAPPER_CLK25_DIVIDER_1 => GT_CLK25_DIVIDER, 00718 WRAPPER_PLL_DIVSEL_FB_0 => GT_PLL_DIVSEL_FB, 00719 WRAPPER_PLL_DIVSEL_FB_1 => GT_PLL_DIVSEL_FB, 00720 WRAPPER_PLL_DIVSEL_REF_0 => GT_PLL_DIVSEL_REF, 00721 WRAPPER_PLL_DIVSEL_REF_1 => GT_PLL_DIVSEL_REF, 00722 WRAPPER_SIMULATION => SIM_INT(FAST_TRAIN) 00723 ) 00724 port map ( 00725 00726 ------------------------ Loopback and Powerdown Ports ---------------------- 00727 TILE0_RXPOWERDOWN0_IN => gt_power_down, 00728 TILE0_RXPOWERDOWN1_IN => "10", 00729 TILE0_TXPOWERDOWN0_IN => gt_power_down, 00730 TILE0_TXPOWERDOWN1_IN => "10", 00731 --------------------------------- PLL Ports -------------------------------- 00732 TILE0_CLK00_IN => sys_clk, 00733 TILE0_CLK01_IN => '0', 00734 TILE0_GTPRESET0_IN => sys_reset, 00735 TILE0_GTPRESET1_IN => '1', 00736 TILE0_PLLLKDET0_OUT => gt_plllkdet_out, 00737 TILE0_PLLLKDET1_OUT => OPEN, 00738 TILE0_RESETDONE0_OUT => gt_reset_done, 00739 TILE0_RESETDONE1_OUT => OPEN, 00740 ----------------------- Receive Ports - 8b10b Decoder ---------------------- 00741 TILE0_RXCHARISK0_OUT(1) => rx_char_is_k(0), 00742 TILE0_RXCHARISK0_OUT(0) => rx_char_is_k(1), 00743 TILE0_RXCHARISK1_OUT => OPEN, 00744 TILE0_RXDISPERR0_OUT => OPEN, 00745 TILE0_RXDISPERR1_OUT => OPEN, 00746 TILE0_RXNOTINTABLE0_OUT => OPEN, 00747 TILE0_RXNOTINTABLE1_OUT => OPEN, 00748 ---------------------- Receive Ports - Clock Correction -------------------- 00749 TILE0_RXCLKCORCNT0_OUT => OPEN, 00750 TILE0_RXCLKCORCNT1_OUT => OPEN, 00751 --------------- Receive Ports - Comma Detection and Alignment -------------- 00752 TILE0_RXENMCOMMAALIGN0_IN => '1', 00753 TILE0_RXENMCOMMAALIGN1_IN => '1', 00754 TILE0_RXENPCOMMAALIGN0_IN => '1', 00755 TILE0_RXENPCOMMAALIGN1_IN => '1', 00756 ------------------- Receive Ports - RX Data Path interface ----------------- 00757 TILE0_RXDATA0_OUT(15 downto 8) => rx_data(7 downto 0), 00758 TILE0_RXDATA0_OUT(7 downto 0) => rx_data(15 downto 8), 00759 TILE0_RXDATA1_OUT => OPEN, 00760 TILE0_RXRESET0_IN => rxreset, 00761 TILE0_RXRESET1_IN => '1', 00762 TILE0_RXUSRCLK0_IN => mgt_clk_2x, 00763 TILE0_RXUSRCLK1_IN => '0', 00764 TILE0_RXUSRCLK20_IN => mgt_clk, 00765 TILE0_RXUSRCLK21_IN => '0', 00766 ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ 00767 TILE0_GATERXELECIDLE0_IN => '0', 00768 TILE0_GATERXELECIDLE1_IN => '0', 00769 TILE0_IGNORESIGDET0_IN => '0', 00770 TILE0_IGNORESIGDET1_IN => '0', 00771 TILE0_RXELECIDLE0_OUT => rx_enter_elecidle, 00772 TILE0_RXELECIDLE1_OUT => OPEN, 00773 TILE0_RXN0_IN => pci_exp_rxn, 00774 TILE0_RXN1_IN => '0', 00775 TILE0_RXP0_IN => pci_exp_rxp, 00776 TILE0_RXP1_IN => '0', 00777 ----------- Receive Ports - RX Elastic Buffer and Phase Alignment ---------- 00778 TILE0_RXSTATUS0_OUT => rx_status, 00779 TILE0_RXSTATUS1_OUT => OPEN, 00780 -------------- Receive Ports - RX Pipe Control for PCI Express ------------- 00781 TILE0_PHYSTATUS0_OUT => phystatus, 00782 TILE0_PHYSTATUS1_OUT => OPEN, 00783 TILE0_RXVALID0_OUT => gt_rx_valid, 00784 TILE0_RXVALID1_OUT => OPEN, 00785 -------------------- Receive Ports - RX Polarity Control ------------------- 00786 TILE0_RXPOLARITY0_IN => rx_polarity, 00787 TILE0_RXPOLARITY1_IN => '0', 00788 ---------------------------- TX/RX Datapath Ports -------------------------- 00789 TILE0_GTPCLKOUT0_OUT => gt_refclk_out, 00790 TILE0_GTPCLKOUT1_OUT => OPEN, 00791 ------------------- Transmit Ports - 8b10b Encoder Control ----------------- 00792 TILE0_TXCHARDISPMODE0_IN(1) => tx_char_disp_mode(0), 00793 TILE0_TXCHARDISPMODE0_IN(0) => tx_char_disp_mode(1), 00794 TILE0_TXCHARDISPMODE1_IN(1) => '0', 00795 TILE0_TXCHARDISPMODE1_IN(0) => '0', 00796 TILE0_TXCHARISK0_IN(1) => tx_char_is_k(0), 00797 TILE0_TXCHARISK0_IN(0) => tx_char_is_k(1), 00798 TILE0_TXCHARISK1_IN(1) => '0', 00799 TILE0_TXCHARISK1_IN(0) => '0', 00800 ------------------ Transmit Ports - TX Data Path interface ----------------- 00801 TILE0_TXDATA0_IN(15 downto 8) => tx_data(7 downto 0), 00802 TILE0_TXDATA0_IN(7 downto 0) => tx_data(15 downto 8), 00803 TILE0_TXDATA1_IN(15 downto 8) => x"00", 00804 TILE0_TXDATA1_IN(7 downto 0) => x"00", 00805 TILE0_TXUSRCLK0_IN => mgt_clk_2x, 00806 TILE0_TXUSRCLK1_IN => '0', 00807 TILE0_TXUSRCLK20_IN => mgt_clk, 00808 TILE0_TXUSRCLK21_IN => '0', 00809 --------------- Transmit Ports - TX Driver and OOB signalling -------------- 00810 TILE0_TXN0_OUT => pci_exp_txn, 00811 TILE0_TXN1_OUT => OPEN, 00812 TILE0_TXP0_OUT => pci_exp_txp, 00813 TILE0_TXP1_OUT => OPEN, 00814 ----------------- Transmit Ports - TX Ports for PCI Express ---------------- 00815 TILE0_TXDETECTRX0_IN => tx_rcvr_det, 00816 TILE0_TXDETECTRX1_IN => '0', 00817 TILE0_TXELECIDLE0_IN => gt_tx_elec_idle, 00818 TILE0_TXELECIDLE1_IN => '0' ); 00819 00820 -- Generate the reset for the PLL 00821 pll_rst <= (not gt_plllkdet_out) or (not sys_reset_n); 00822 00823 --------------------------------------------------------------------------- 00824 -- Generate the connection between PCIE_A1 block and the GTPA1_DUAL. When 00825 -- the parameter GTP_SEL is 0, connect to PIPEA, when it is a 1, connect to 00826 -- PIPEB. 00827 --------------------------------------------------------------------------- 00828 PIPE_A_SEL : if (GTP_SEL = 0) generate 00829 -- Signals from GTPA1_DUAL to PCIE_A1 00830 pipe_rx_charisk_a <= rx_char_is_k; 00831 pipe_rx_data_a <= rx_data; 00832 pipe_rx_enter_elec_idle_a <= rx_enter_elecidle; 00833 pipe_rx_status_a <= rx_status; 00834 pipe_phy_status_a <= phystatus; 00835 pipe_gt_reset_done_a <= gt_reset_done; 00836 00837 -- Unused PCIE_A1 inputs 00838 pipe_rx_charisk_b <= "00"; 00839 pipe_rx_data_b <= x"0000"; 00840 pipe_rx_enter_elec_idle_b <= '0'; 00841 pipe_rx_status_b <= "000"; 00842 pipe_phy_status_b <= '0'; 00843 pipe_gt_reset_done_b <= '0'; 00844 00845 -- Signals from PCIE_A1 to GTPA1_DUAL 00846 rx_polarity <= pipe_rx_polarity_a; 00847 tx_char_disp_mode <= pipe_tx_char_disp_mode_a; 00848 tx_char_is_k <= pipe_tx_char_is_k_a; 00849 tx_rcvr_det <= pipe_tx_rcvr_det_a; 00850 tx_data <= pipe_tx_data_a; 00851 gt_tx_elec_idle <= pipe_gt_tx_elec_idle_a; 00852 gt_power_down <= pipe_gt_power_down_a; 00853 rxreset <= pipe_rxreset_a; 00854 end generate PIPE_A_SEL; 00855 00856 PIPE_B_SEL : if (GTP_SEL = 1) generate 00857 -- Signals from GTPA1_DUAL to PCIE_A1 00858 pipe_rx_charisk_b <= rx_char_is_k; 00859 pipe_rx_data_b <= rx_data; 00860 pipe_rx_enter_elec_idle_b <= rx_enter_elecidle; 00861 pipe_rx_status_b <= rx_status; 00862 pipe_phy_status_b <= phystatus; 00863 pipe_gt_reset_done_b <= gt_reset_done; 00864 00865 -- Unused PCIE_A1 inputs 00866 pipe_rx_charisk_a <= "00"; 00867 pipe_rx_data_a <= x"0000"; 00868 pipe_rx_enter_elec_idle_a <= '0'; 00869 pipe_rx_status_a <= "000"; 00870 pipe_phy_status_a <= '0'; 00871 pipe_gt_reset_done_a <= '0'; 00872 00873 -- Signals from PCIE_A1 to GTPA1_DUAL 00874 rx_polarity <= pipe_rx_polarity_b; 00875 tx_char_disp_mode <= pipe_tx_char_disp_mode_b; 00876 tx_char_is_k <= pipe_tx_char_is_k_b; 00877 tx_rcvr_det <= pipe_tx_rcvr_det_b; 00878 tx_data <= pipe_tx_data_b; 00879 gt_tx_elec_idle <= pipe_gt_tx_elec_idle_b; 00880 gt_power_down <= pipe_gt_power_down_b; 00881 rxreset <= pipe_rxreset_b; 00882 end generate PIPE_B_SEL; 00883 00884 --------------------------------------------------------------- 00885 -- Integrated Endpoint Block for PCI Express Instance (PCIE_A1) 00886 --------------------------------------------------------------- 00887 00888 PCIE_A1_inst : PCIE_A1 00889 generic map ( 00890 BAR0 => BAR0, 00891 BAR1 => BAR1, 00892 BAR2 => BAR2, 00893 BAR3 => BAR3, 00894 BAR4 => BAR4, 00895 BAR5 => BAR5, 00896 CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER, 00897 CLASS_CODE => CLASS_CODE, 00898 DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY, 00899 DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY, 00900 DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED, 00901 DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED, 00902 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT, 00903 DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR, 00904 DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING, 00905 DISABLE_ID_CHECK => DISABLE_ID_CHECK, 00906 DISABLE_SCRAMBLING => DISABLE_SCRAMBLING, 00907 ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM, 00908 EXPANSION_ROM => EXPANSION_ROM, 00909 FAST_TRAIN => FAST_TRAIN, 00910 GTP_SEL => GTP_SEL, 00911 LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT, 00912 LINK_CAP_L0S_EXIT_LATENCY => LINK_CAP_L0S_EXIT_LATENCY, 00913 LINK_CAP_L1_EXIT_LATENCY => LINK_CAP_L1_EXIT_LATENCY, 00914 LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG, 00915 LL_ACK_TIMEOUT => LL_ACK_TIMEOUT, 00916 LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN, 00917 LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT, 00918 LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN, 00919 MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION, 00920 MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP, 00921 PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION, 00922 PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE, 00923 PCIE_CAP_INT_MSG_NUM => PCIE_CAP_INT_MSG_NUM, 00924 PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED, 00925 PCIE_GENERIC => PCIE_GENERIC, 00926 PLM_AUTO_CONFIG => PLM_AUTO_CONFIG, 00927 PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT, 00928 PM_CAP_DSI => PM_CAP_DSI, 00929 PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT, 00930 PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT, 00931 PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK, 00932 PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT, 00933 PM_CAP_VERSION => PM_CAP_VERSION, 00934 PM_DATA_SCALE0 => PM_DATA_SCALE0, 00935 PM_DATA_SCALE1 => PM_DATA_SCALE1, 00936 PM_DATA_SCALE2 => PM_DATA_SCALE2, 00937 PM_DATA_SCALE3 => PM_DATA_SCALE3, 00938 PM_DATA_SCALE4 => PM_DATA_SCALE4, 00939 PM_DATA_SCALE5 => PM_DATA_SCALE5, 00940 PM_DATA_SCALE6 => PM_DATA_SCALE6, 00941 PM_DATA_SCALE7 => PM_DATA_SCALE7, 00942 PM_DATA0 => PM_DATA0, 00943 PM_DATA1 => PM_DATA1, 00944 PM_DATA2 => PM_DATA2, 00945 PM_DATA3 => PM_DATA3, 00946 PM_DATA4 => PM_DATA4, 00947 PM_DATA5 => PM_DATA5, 00948 PM_DATA6 => PM_DATA6, 00949 PM_DATA7 => PM_DATA7, 00950 SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT, 00951 SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT, 00952 SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT, 00953 TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY, 00954 TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY, 00955 TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY, 00956 TL_TFC_DISABLE => TL_TFC_DISABLE, 00957 TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE, 00958 TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY, 00959 TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY, 00960 USR_CFG => USR_CFG, 00961 USR_EXT_CFG => USR_EXT_CFG, 00962 VC0_CPL_INFINITE => VC0_CPL_INFINITE, 00963 VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT, 00964 VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD, 00965 VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH, 00966 VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH, 00967 VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD, 00968 VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH, 00969 VC0_TX_LASTPACKET => VC0_TX_LASTPACKET 00970 ) 00971 port map ( 00972 CFGBUSNUMBER => cfg_bus_number, 00973 CFGCOMMANDBUSMASTERENABLE => cfg_command_bus_master_enable, 00974 CFGCOMMANDINTERRUPTDISABLE => cfg_command_interrupt_disable, 00975 CFGCOMMANDIOENABLE => cfg_command_io_enable, 00976 CFGCOMMANDMEMENABLE => cfg_command_mem_enable, 00977 CFGCOMMANDSERREN => cfg_command_serr_en, 00978 CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en, 00979 CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en, 00980 CFGDEVCONTROLENABLERO => cfg_dev_control_enable_ro, 00981 CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en, 00982 CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en, 00983 CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_max_payload, 00984 CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req, 00985 CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en, 00986 CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_no_snoop_en, 00987 CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en, 00988 CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en , 00989 CFGDEVICENUMBER => cfg_device_number, 00990 CFGDEVID => w_cfg_dev_id, 00991 CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected , 00992 CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected , 00993 CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected , 00994 CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected, 00995 CFGDO => cfg_do, 00996 CFGDSN => cfg_dsn, 00997 CFGDWADDR => cfg_dwaddr, 00998 CFGERRCORN => cfg_err_cor_n, 00999 CFGERRCPLABORTN => cfg_err_cpl_abort_n, 01000 CFGERRCPLRDYN => cfg_err_cpl_rdy_n, 01001 CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n, 01002 CFGERRECRCN => cfg_err_ecrc_n, 01003 CFGERRLOCKEDN => cfg_err_locked_n, 01004 CFGERRPOSTEDN => cfg_err_posted_n, 01005 CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header, 01006 CFGERRURN => cfg_err_ur_n, 01007 CFGFUNCTIONNUMBER => cfg_function_number, 01008 CFGINTERRUPTASSERTN => cfg_interrupt_assert_n, 01009 CFGINTERRUPTDI => cfg_interrupt_di, 01010 CFGINTERRUPTDO => cfg_interrupt_do, 01011 CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable, 01012 CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable, 01013 CFGINTERRUPTN => cfg_interrupt_n, 01014 CFGINTERRUPTRDYN => cfg_interrupt_rdy_n, 01015 CFGLINKCONTOLRCB => cfg_link_control_rcb, 01016 CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control, 01017 CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock, 01018 CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync, 01019 CFGLTSSMSTATE => cfg_ltssm_state, 01020 CFGPCIELINKSTATEN => cfg_pcie_link_state_n, 01021 CFGPMWAKEN => cfg_pm_wake_n, 01022 CFGRDENN => cfg_rd_en_n, 01023 CFGRDWRDONEN => cfg_rd_wr_done_n, 01024 CFGREVID => w_cfg_rev_id, 01025 CFGSUBSYSID => w_cfg_subsys_id, 01026 CFGSUBSYSVENID => w_cfg_subsys_ven_id, 01027 CFGTOTURNOFFN => cfg_to_turnoff_n, 01028 CFGTRNPENDINGN => cfg_trn_pending_n, 01029 CFGTURNOFFOKN => cfg_turnoff_ok_n, 01030 CFGVENID => w_cfg_ven_id, 01031 CLOCKLOCKED => clock_locked, 01032 DBGBADDLLPSTATUS => dbg_bad_dllp_status, 01033 DBGBADTLPLCRC => dbg_bad_tlp_lcrc, 01034 DBGBADTLPSEQNUM => dbg_bad_tlp_seq_num, 01035 DBGBADTLPSTATUS => dbg_bad_tlp_status, 01036 DBGDLPROTOCOLSTATUS => dbg_dl_protocol_status, 01037 DBGFCPROTOCOLERRSTATUS => dbg_fc_protocol_err_status, 01038 DBGMLFRMDLENGTH => dbg_mlfrmd_length, 01039 DBGMLFRMDMPS => dbg_mlfrmd_mps, 01040 DBGMLFRMDTCVC => dbg_mlfrmd_tcvc, 01041 DBGMLFRMDTLPSTATUS => dbg_mlfrmd_tlp_status, 01042 DBGMLFRMDUNRECTYPE => dbg_mlfrmd_unrec_type, 01043 DBGPOISTLPSTATUS => dbg_poistlpstatus, 01044 DBGRCVROVERFLOWSTATUS => dbg_rcvr_overflow_status, 01045 DBGREGDETECTEDCORRECTABLE => dbg_reg_detected_correctable, 01046 DBGREGDETECTEDFATAL => dbg_reg_detected_fatal, 01047 DBGREGDETECTEDNONFATAL => dbg_reg_detected_non_fatal, 01048 DBGREGDETECTEDUNSUPPORTED => dbg_reg_detected_unsupported, 01049 DBGRPLYROLLOVERSTATUS => dbg_rply_rollover_status, 01050 DBGRPLYTIMEOUTSTATUS => dbg_rply_timeout_status, 01051 DBGURNOBARHIT => dbg_ur_no_bar_hit, 01052 DBGURPOISCFGWR => dbg_ur_pois_cfg_wr, 01053 DBGURSTATUS => dbg_ur_status, 01054 DBGURUNSUPMSG => dbg_ur_unsup_msg, 01055 MGTCLK => mgt_clk, 01056 MIMRXRADDR => mim_rx_raddr, 01057 MIMRXRDATA => mim_rx_rdata, 01058 MIMRXREN => mim_rx_ren, 01059 MIMRXWADDR => mim_rx_waddr, 01060 MIMRXWDATA => mim_rx_wdata, 01061 MIMRXWEN => mim_rx_wen, 01062 MIMTXRADDR => mim_tx_raddr, 01063 MIMTXRDATA => mim_tx_rdata, 01064 MIMTXREN => mim_tx_ren, 01065 MIMTXWADDR => mim_tx_waddr, 01066 MIMTXWDATA => mim_tx_wdata, 01067 MIMTXWEN => mim_tx_wen, 01068 PIPEGTPOWERDOWNA => pipe_gt_power_down_a, 01069 PIPEGTPOWERDOWNB => pipe_gt_power_down_b, 01070 PIPEGTRESETDONEA => pipe_gt_reset_done_a, 01071 PIPEGTRESETDONEB => pipe_gt_reset_done_b, 01072 PIPEGTTXELECIDLEA => pipe_gt_tx_elec_idle_a, 01073 PIPEGTTXELECIDLEB => pipe_gt_tx_elec_idle_b, 01074 PIPEPHYSTATUSA => pipe_phy_status_a, 01075 PIPEPHYSTATUSB => pipe_phy_status_b, 01076 PIPERXCHARISKA => pipe_rx_charisk_a, 01077 PIPERXCHARISKB => pipe_rx_charisk_b, 01078 PIPERXDATAA => pipe_rx_data_a, 01079 PIPERXDATAB => pipe_rx_data_b, 01080 PIPERXENTERELECIDLEA => pipe_rx_enter_elec_idle_a, 01081 PIPERXENTERELECIDLEB => pipe_rx_enter_elec_idle_b, 01082 PIPERXPOLARITYA => pipe_rx_polarity_a, 01083 PIPERXPOLARITYB => pipe_rx_polarity_b, 01084 PIPERXRESETA => pipe_rxreset_a, 01085 PIPERXRESETB => pipe_rxreset_b, 01086 PIPERXSTATUSA => pipe_rx_status_a, 01087 PIPERXSTATUSB => pipe_rx_status_b, 01088 PIPETXCHARDISPMODEA => pipe_tx_char_disp_mode_a, 01089 PIPETXCHARDISPMODEB => pipe_tx_char_disp_mode_b, 01090 PIPETXCHARDISPVALA => pipe_tx_char_disp_val_a, 01091 PIPETXCHARDISPVALB => pipe_tx_char_disp_val_b, 01092 PIPETXCHARISKA => pipe_tx_char_is_k_a, 01093 PIPETXCHARISKB => pipe_tx_char_is_k_b, 01094 PIPETXDATAA => pipe_tx_data_a, 01095 PIPETXDATAB => pipe_tx_data_b, 01096 PIPETXRCVRDETA => pipe_tx_rcvr_det_a, 01097 PIPETXRCVRDETB => pipe_tx_rcvr_det_b, 01098 RECEIVEDHOTRESET => received_hot_reset, 01099 SYSRESETN => sys_reset_n, 01100 TRNFCCPLD => trn_fc_cpld, 01101 TRNFCCPLH => trn_fc_cplh, 01102 TRNFCNPD => trn_fc_npd, 01103 TRNFCNPH => trn_fc_nph, 01104 TRNFCPD => trn_fc_pd, 01105 TRNFCPH => trn_fc_ph, 01106 TRNFCSEL => trn_fc_sel, 01107 TRNLNKUPN => trn_lnk_up_n, 01108 TRNRBARHITN => trn_rbar_hit_n, 01109 TRNRD => trn_rd, 01110 TRNRDSTRDYN => trn_rdst_rdy_n, 01111 TRNREOFN => trn_reof_n, 01112 TRNRERRFWDN => trn_rerrfwd_n, 01113 TRNRNPOKN => trn_rnp_ok_n, 01114 TRNRSOFN => trn_rsof_n, 01115 TRNRSRCDSCN => trn_rsrc_dsc_n, 01116 TRNRSRCRDYN => trn_rsrc_rdy_n, 01117 TRNTBUFAV => trn_tbuf_av, 01118 TRNTCFGGNTN => trn_tcfg_gnt_n, 01119 TRNTCFGREQN => trn_tcfg_req_n, 01120 TRNTD => trn_td, 01121 TRNTDSTRDYN => trn_tdst_rdy_n, 01122 TRNTEOFN => trn_teof_n, 01123 TRNTERRDROPN => trn_terr_drop_n, 01124 TRNTERRFWDN => trn_terrfwd_n, 01125 TRNTSOFN => trn_tsof_n, 01126 TRNTSRCDSCN => trn_tsrc_dsc_n, 01127 TRNTSRCRDYN => trn_tsrc_rdy_n, 01128 TRNTSTRN => trn_tstr_n, 01129 USERCLK => trn_clk_c, 01130 USERRSTN => trn_reset_n_c 01131 ); 01132 01133 ---------------------------------------------------- 01134 -- Recreate wrapper outputs from the PCIE_A1 signals 01135 ---------------------------------------------------- 01136 cfg_status <= x"0000"; 01137 01138 cfg_command <= "00000" & 01139 cfg_command_interrupt_disable & 01140 "0" & 01141 cfg_command_serr_en & 01142 "00000" & 01143 cfg_command_bus_master_enable & 01144 cfg_command_mem_enable & 01145 cfg_command_io_enable; 01146 01147 cfg_dstatus <= "0000000000" & 01148 not cfg_trn_pending_n & 01149 '0' & 01150 cfg_dev_status_ur_detected & 01151 cfg_dev_status_fatal_err_detected & 01152 cfg_dev_status_nonfatal_err_detected & 01153 cfg_dev_status_corr_err_detected; 01154 01155 cfg_dcommand <= '0' & 01156 cfg_dev_control_max_read_req & 01157 cfg_dev_control_no_snoop_en & 01158 cfg_dev_control_aux_power_en & 01159 cfg_dev_control_phantom_en & 01160 cfg_dev_control_ext_tag_en & 01161 cfg_dev_control_max_payload & 01162 cfg_dev_control_enable_ro & 01163 cfg_dev_control_ur_err_reporting_en & 01164 cfg_dev_control_fatal_err_reporting_en & 01165 cfg_dev_control_non_fatal_reporting_en & 01166 cfg_dev_control_corr_err_reporting_en; 01167 01168 cfg_lstatus <= x"0011"; 01169 01170 cfg_lcommand <= x"00" & 01171 cfg_link_control_extended_sync & 01172 cfg_link_control_common_clock & 01173 "00" & 01174 cfg_link_control_rcb & 01175 '0' & 01176 cfg_link_control_aspm_control; 01177 01178 end rtl;
1.7.4