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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : cl_v6pcie_x4.vhd 00052 -- Version : 2.3 00053 -- Description: Virtex6 solution wrapper : Endpoint for PCI Express 00054 -- 00055 -- 00056 -- 00057 -------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 use ieee.std_logic_unsigned.all; 00062 00063 library unisim; 00064 use unisim.vcomponents.all; 00065 00066 entity cl_v6pcie_x4 is 00067 generic ( 00068 PCIE_DRP_ENABLE : boolean := FALSE; 00069 ALLOW_X8_GEN2 : boolean := FALSE; 00070 BAR0 : bit_vector := X"FFE00000"; 00071 BAR1 : bit_vector := X"FFE00000"; 00072 BAR2 : bit_vector := X"00000000"; 00073 BAR3 : bit_vector := X"00000000"; 00074 BAR4 : bit_vector := X"00000000"; 00075 BAR5 : bit_vector := X"00000000"; 00076 00077 CARDBUS_CIS_POINTER : bit_vector := X"00000000"; 00078 CLASS_CODE : bit_vector := X"FFFFFF"; 00079 CMD_INTX_IMPLEMENTED : boolean := TRUE; 00080 CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE; 00081 CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"2"; 00082 00083 DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0; 00084 DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; 00085 DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; 00086 DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 1; 00087 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; 00088 DEVICE_ID : bit_vector := X"5507"; 00089 00090 DISABLE_LANE_REVERSAL : boolean := TRUE; 00091 DISABLE_SCRAMBLING : boolean := FALSE; 00092 DSN_BASE_PTR : bit_vector := X"0"; 00093 DSN_CAP_NEXTPTR : bit_vector := X"000"; 00094 DSN_CAP_ON : boolean := FALSE; 00095 00096 ENABLE_MSG_ROUTE : bit_vector := "00000000000"; 00097 ENABLE_RX_TD_ECRC_TRIM : boolean := TRUE; 00098 EXPANSION_ROM : bit_vector := X"00000000"; 00099 EXT_CFG_CAP_PTR : bit_vector := X"3F"; 00100 EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF"; 00101 HEADER_TYPE : bit_vector := X"00"; 00102 INTERRUPT_PIN : bit_vector := X"1"; 00103 00104 LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE; 00105 LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE; 00106 LINK_CAP_MAX_LINK_SPEED : bit_vector := X"2"; 00107 LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"04"; 00108 LINK_CAP_MAX_LINK_WIDTH_int : integer := 4; 00109 LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE; 00110 00111 LINK_CTRL2_DEEMPHASIS : boolean := FALSE; 00112 LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE; 00113 LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2"; 00114 LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE; 00115 00116 LL_ACK_TIMEOUT : bit_vector := X"0000"; 00117 LL_ACK_TIMEOUT_EN : boolean := FALSE; 00118 LL_ACK_TIMEOUT_FUNC : integer := 0; 00119 LL_REPLAY_TIMEOUT : bit_vector := X"0026"; 00120 LL_REPLAY_TIMEOUT_EN : boolean := TRUE; 00121 LL_REPLAY_TIMEOUT_FUNC : integer := 1; 00122 00123 LTSSM_MAX_LINK_WIDTH : bit_vector := X"04"; 00124 MSI_CAP_MULTIMSGCAP : integer := 0; 00125 MSI_CAP_MULTIMSG_EXTENSION : integer := 0; 00126 MSI_CAP_ON : boolean := FALSE; 00127 MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := FALSE; 00128 MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE; 00129 00130 MSIX_CAP_ON : boolean := FALSE; 00131 MSIX_CAP_PBA_BIR : integer := 0; 00132 MSIX_CAP_PBA_OFFSET : bit_vector := X"0"; 00133 MSIX_CAP_TABLE_BIR : integer := 0; 00134 MSIX_CAP_TABLE_OFFSET : bit_vector := X"0"; 00135 MSIX_CAP_TABLE_SIZE : bit_vector := X"000"; 00136 00137 PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0"; 00138 PCIE_CAP_INT_MSG_NUM : bit_vector := X"1"; 00139 PCIE_CAP_NEXTPTR : bit_vector := X"00"; 00140 PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages; 1 - 1 stage; 2 - 2 stages 00141 00142 PM_CAP_DSI : boolean := FALSE; 00143 PM_CAP_D1SUPPORT : boolean := FALSE; 00144 PM_CAP_D2SUPPORT : boolean := FALSE; 00145 PM_CAP_NEXTPTR : bit_vector := X"60"; 00146 PM_CAP_PMESUPPORT : bit_vector := X"0F"; 00147 PM_CSR_NOSOFTRST : boolean := TRUE; 00148 00149 PM_DATA_SCALE0 : bit_vector := X"0"; 00150 PM_DATA_SCALE1 : bit_vector := X"0"; 00151 PM_DATA_SCALE2 : bit_vector := X"0"; 00152 PM_DATA_SCALE3 : bit_vector := X"0"; 00153 PM_DATA_SCALE4 : bit_vector := X"0"; 00154 PM_DATA_SCALE5 : bit_vector := X"0"; 00155 PM_DATA_SCALE6 : bit_vector := X"0"; 00156 PM_DATA_SCALE7 : bit_vector := X"0"; 00157 00158 PM_DATA0 : bit_vector := X"00"; 00159 PM_DATA1 : bit_vector := X"00"; 00160 PM_DATA2 : bit_vector := X"00"; 00161 PM_DATA3 : bit_vector := X"00"; 00162 PM_DATA4 : bit_vector := X"00"; 00163 PM_DATA5 : bit_vector := X"00"; 00164 PM_DATA6 : bit_vector := X"00"; 00165 PM_DATA7 : bit_vector := X"00"; 00166 00167 REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz 00168 REVISION_ID : bit_vector := X"20"; 00169 SPARE_BIT0 : integer := 0; 00170 SUBSYSTEM_ID : bit_vector := X"0002"; 00171 SUBSYSTEM_VENDOR_ID : bit_vector := X"4953"; 00172 00173 TL_RX_RAM_RADDR_LATENCY : integer := 0; 00174 TL_RX_RAM_RDATA_LATENCY : integer := 2; 00175 TL_RX_RAM_WRITE_LATENCY : integer := 0; 00176 TL_TX_RAM_RADDR_LATENCY : integer := 0; 00177 TL_TX_RAM_RDATA_LATENCY : integer := 2; 00178 TL_TX_RAM_WRITE_LATENCY : integer := 0; 00179 00180 UPCONFIG_CAPABLE : boolean := TRUE; 00181 USER_CLK_FREQ : integer := 3; 00182 VC_BASE_PTR : bit_vector := X"0"; 00183 VC_CAP_NEXTPTR : bit_vector := X"000"; 00184 VC_CAP_ON : boolean := FALSE; 00185 VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE; 00186 00187 VC0_CPL_INFINITE : boolean := TRUE; 00188 VC0_RX_RAM_LIMIT : bit_vector := X"3FF"; 00189 VC0_TOTAL_CREDITS_CD : integer := 378; 00190 VC0_TOTAL_CREDITS_CH : integer := 36; 00191 VC0_TOTAL_CREDITS_NPH : integer := 12; 00192 VC0_TOTAL_CREDITS_PD : integer := 32; 00193 VC0_TOTAL_CREDITS_PH : integer := 32; 00194 VC0_TX_LASTPACKET : integer := 28; 00195 00196 VENDOR_ID : bit_vector := X"4953"; 00197 VSEC_BASE_PTR : bit_vector := X"0"; 00198 VSEC_CAP_NEXTPTR : bit_vector := X"000"; 00199 VSEC_CAP_ON : boolean := FALSE; 00200 00201 AER_BASE_PTR : bit_vector := X"128"; 00202 AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE; 00203 AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE; 00204 AER_CAP_ID : bit_vector := X"0001"; 00205 AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0a"; 00206 AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15"; 00207 AER_CAP_NEXTPTR : bit_vector := X"160"; 00208 AER_CAP_ON : boolean := FALSE; 00209 AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE; 00210 AER_CAP_VERSION : bit_vector := X"1"; 00211 00212 CAPABILITIES_PTR : bit_vector := X"40"; 00213 CRM_MODULE_RSTS : bit_vector := X"00"; 00214 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE; 00215 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE; 00216 DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE; 00217 DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; 00218 DEV_CAP_RSVD_14_12 : integer := 0; 00219 DEV_CAP_RSVD_17_16 : integer := 0; 00220 DEV_CAP_RSVD_31_29 : integer := 0; 00221 DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE; 00222 00223 DISABLE_ASPM_L1_TIMER : boolean := FALSE; 00224 DISABLE_BAR_FILTERING : boolean := FALSE; 00225 DISABLE_ID_CHECK : boolean := FALSE; 00226 DISABLE_RX_TC_FILTER : boolean := FALSE; 00227 DNSTREAM_LINK_NUM : bit_vector := X"00"; 00228 00229 DSN_CAP_ID : bit_vector := X"0003"; 00230 DSN_CAP_VERSION : bit_vector := X"1"; 00231 ENTER_RVRY_EI_L0 : boolean := TRUE; 00232 INFER_EI : bit_vector := X"0c"; 00233 IS_SWITCH : boolean := FALSE; 00234 00235 LAST_CONFIG_DWORD : bit_vector := X"3FF"; 00236 LINK_CAP_ASPM_SUPPORT : integer := 1; 00237 LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE; 00238 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7; 00239 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7; 00240 LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7; 00241 LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7; 00242 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7; 00243 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7; 00244 LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7; 00245 LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7; 00246 LINK_CAP_RSVD_23_22 : integer := 0; 00247 LINK_CONTROL_RCB : integer := 0; 00248 00249 MSI_BASE_PTR : bit_vector := X"48"; 00250 MSI_CAP_ID : bit_vector := X"05"; 00251 MSI_CAP_NEXTPTR : bit_vector := X"60"; 00252 MSIX_BASE_PTR : bit_vector := X"9c"; 00253 MSIX_CAP_ID : bit_vector := X"11"; 00254 MSIX_CAP_NEXTPTR : bit_vector := X"00"; 00255 N_FTS_COMCLK_GEN1 : integer := 255; 00256 N_FTS_COMCLK_GEN2 : integer := 254; 00257 N_FTS_GEN1 : integer := 255; 00258 N_FTS_GEN2 : integer := 255; 00259 00260 PCIE_BASE_PTR : bit_vector := X"60"; 00261 PCIE_CAP_CAPABILITY_ID : bit_vector := X"10"; 00262 PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2"; 00263 PCIE_CAP_ON : boolean := TRUE; 00264 PCIE_CAP_RSVD_15_14 : integer := 0; 00265 PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; 00266 PCIE_REVISION : integer := 2; 00267 PGL0_LANE : integer := 0; 00268 PGL1_LANE : integer := 1; 00269 PGL2_LANE : integer := 2; 00270 PGL3_LANE : integer := 3; 00271 PGL4_LANE : integer := 4; 00272 PGL5_LANE : integer := 5; 00273 PGL6_LANE : integer := 6; 00274 PGL7_LANE : integer := 7; 00275 PL_AUTO_CONFIG : integer := 0; 00276 PL_FAST_TRAIN : boolean := FALSE; 00277 00278 PM_BASE_PTR : bit_vector := X"40"; 00279 PM_CAP_AUXCURRENT : integer := 0; 00280 PM_CAP_ID : bit_vector := X"01"; 00281 PM_CAP_ON : boolean := TRUE; 00282 PM_CAP_PME_CLOCK : boolean := FALSE; 00283 PM_CAP_RSVD_04 : integer := 0; 00284 PM_CAP_VERSION : integer := 3; 00285 PM_CSR_BPCCEN : boolean := FALSE; 00286 PM_CSR_B2B3 : boolean := FALSE; 00287 00288 RECRC_CHK : integer := 0; 00289 RECRC_CHK_TRIM : boolean := FALSE; 00290 ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE; 00291 SELECT_DLL_IF : boolean := FALSE; 00292 SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; 00293 SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; 00294 SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE; 00295 SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE; 00296 SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE; 00297 SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE; 00298 SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE; 00299 SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000"; 00300 SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE; 00301 SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; 00302 SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0; 00303 SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00"; 00304 SPARE_BIT1 : integer := 0; 00305 SPARE_BIT2 : integer := 0; 00306 SPARE_BIT3 : integer := 0; 00307 SPARE_BIT4 : integer := 0; 00308 SPARE_BIT5 : integer := 0; 00309 SPARE_BIT6 : integer := 0; 00310 SPARE_BIT7 : integer := 0; 00311 SPARE_BIT8 : integer := 0; 00312 SPARE_BYTE0 : bit_vector := X"00"; 00313 SPARE_BYTE1 : bit_vector := X"00"; 00314 SPARE_BYTE2 : bit_vector := X"00"; 00315 SPARE_BYTE3 : bit_vector := X"00"; 00316 SPARE_WORD0 : bit_vector := X"00000000"; 00317 SPARE_WORD1 : bit_vector := X"00000000"; 00318 SPARE_WORD2 : bit_vector := X"00000000"; 00319 SPARE_WORD3 : bit_vector := X"00000000"; 00320 00321 TL_RBYPASS : boolean := FALSE; 00322 TL_TFC_DISABLE : boolean := FALSE; 00323 TL_TX_CHECKS_DISABLE : boolean := FALSE; 00324 EXIT_LOOPBACK_ON_EI : boolean := TRUE; 00325 UPSTREAM_FACING : boolean := TRUE; 00326 UR_INV_REQ : boolean := TRUE; 00327 00328 VC_CAP_ID : bit_vector := X"0002"; 00329 VC_CAP_VERSION : bit_vector := X"1"; 00330 VSEC_CAP_HDR_ID : bit_vector := X"1234"; 00331 VSEC_CAP_HDR_LENGTH : bit_vector := X"018"; 00332 VSEC_CAP_HDR_REVISION : bit_vector := X"1"; 00333 VSEC_CAP_ID : bit_vector := X"000b"; 00334 VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE; 00335 VSEC_CAP_VERSION : bit_vector := X"1" 00336 ); 00337 port ( 00338 --------------------------------------------------------- 00339 -- 1. PCI Express (pci_exp) Interface 00340 --------------------------------------------------------- 00341 00342 -- Tx 00343 pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00344 pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00345 00346 -- Rx 00347 pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00348 pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00349 00350 --------------------------------------------------------- 00351 -- 2. Transaction (TRN) Interface 00352 --------------------------------------------------------- 00353 00354 -- Common 00355 user_clk_out : out std_logic; 00356 user_reset_out : out std_logic; 00357 user_lnk_up : out std_logic; 00358 00359 -- Tx 00360 tx_buf_av : out std_logic_vector(5 downto 0); 00361 tx_cfg_req : out std_logic; 00362 tx_err_drop : out std_logic; 00363 00364 s_axis_tx_tready : out std_logic; 00365 s_axis_tx_tdata : in std_logic_vector(63 downto 0); 00366 s_axis_tx_tstrb : in std_logic_vector(7 downto 0); 00367 s_axis_tx_tuser : in std_logic_vector(3 downto 0); 00368 s_axis_tx_tlast : in std_logic; 00369 s_axis_tx_tvalid : in std_logic; 00370 00371 tx_cfg_gnt : in std_logic; 00372 00373 -- Rx 00374 m_axis_rx_tdata : out std_logic_vector(63 downto 0); 00375 m_axis_rx_tstrb : out std_logic_vector(7 downto 0); 00376 m_axis_rx_tlast : out std_logic; 00377 m_axis_rx_tvalid : out std_logic; 00378 m_axis_rx_tuser : out std_logic_vector(21 downto 0); 00379 m_axis_rx_tready : in std_logic; 00380 rx_np_ok : in std_logic; 00381 00382 -- Flow Control 00383 fc_cpld : out std_logic_vector(11 downto 0); 00384 fc_cplh : out std_logic_vector(7 downto 0); 00385 fc_npd : out std_logic_vector(11 downto 0); 00386 fc_nph : out std_logic_vector(7 downto 0); 00387 fc_pd : out std_logic_vector(11 downto 0); 00388 fc_ph : out std_logic_vector(7 downto 0); 00389 fc_sel : in std_logic_vector(2 downto 0); 00390 00391 --------------------------------------------------------- 00392 -- 3. Configuration (CFG) Interface 00393 --------------------------------------------------------- 00394 00395 cfg_do : out std_logic_vector(31 downto 0); 00396 cfg_rd_wr_done : out std_logic; 00397 cfg_di : in std_logic_vector(31 downto 0); 00398 cfg_byte_en : in std_logic_vector(3 downto 0); 00399 cfg_dwaddr : in std_logic_vector(9 downto 0); 00400 cfg_wr_en : in std_logic; 00401 cfg_rd_en : in std_logic; 00402 00403 cfg_err_cor : in std_logic; 00404 cfg_err_ur : in std_logic; 00405 cfg_err_ecrc : in std_logic; 00406 cfg_err_cpl_timeout : in std_logic; 00407 cfg_err_cpl_abort : in std_logic; 00408 cfg_err_cpl_unexpect : in std_logic; 00409 cfg_err_posted : in std_logic; 00410 cfg_err_locked : in std_logic; 00411 cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0); 00412 cfg_err_cpl_rdy : out std_logic; 00413 cfg_interrupt : in std_logic; 00414 cfg_interrupt_rdy : out std_logic; 00415 cfg_interrupt_assert : in std_logic; 00416 cfg_interrupt_di : in std_logic_vector(7 downto 0); 00417 cfg_interrupt_do : out std_logic_vector(7 downto 0); 00418 cfg_interrupt_mmenable : out std_logic_vector(2 downto 0); 00419 cfg_interrupt_msienable : out std_logic; 00420 cfg_interrupt_msixenable : out std_logic; 00421 cfg_interrupt_msixfm : out std_logic; 00422 cfg_turnoff_ok : in std_logic; 00423 cfg_to_turnoff : out std_logic; 00424 cfg_trn_pending : in std_logic; 00425 cfg_pm_wake : in std_logic; 00426 cfg_bus_number : out std_logic_vector(7 downto 0); 00427 cfg_device_number : out std_logic_vector(4 downto 0); 00428 cfg_function_number : out std_logic_vector(2 downto 0); 00429 cfg_status : out std_logic_vector(15 downto 0); 00430 cfg_command : out std_logic_vector(15 downto 0); 00431 cfg_dstatus : out std_logic_vector(15 downto 0); 00432 cfg_dcommand : out std_logic_vector(15 downto 0); 00433 cfg_lstatus : out std_logic_vector(15 downto 0); 00434 cfg_lcommand : out std_logic_vector(15 downto 0); 00435 cfg_dcommand2 : out std_logic_vector(15 downto 0); 00436 cfg_pcie_link_state : out std_logic_vector(2 downto 0); 00437 cfg_dsn : in std_logic_vector(63 downto 0); 00438 cfg_pmcsr_pme_en : out std_logic; 00439 cfg_pmcsr_pme_status : out std_logic; 00440 cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0); 00441 00442 --------------------------------------------------------- 00443 -- 4. Physical Layer Control and Status (PL) Interface 00444 --------------------------------------------------------- 00445 00446 pl_initial_link_width : out std_logic_vector(2 downto 0); 00447 pl_lane_reversal_mode : out std_logic_vector(1 downto 0); 00448 pl_link_gen2_capable : out std_logic; 00449 pl_link_partner_gen2_supported : out std_logic; 00450 pl_link_upcfg_capable : out std_logic; 00451 pl_ltssm_state : out std_logic_vector(5 downto 0); 00452 pl_received_hot_rst : out std_logic; 00453 pl_sel_link_rate : out std_logic; 00454 pl_sel_link_width : out std_logic_vector(1 downto 0); 00455 pl_directed_link_auton : in std_logic; 00456 pl_directed_link_change : in std_logic_vector(1 downto 0); 00457 pl_directed_link_speed : in std_logic; 00458 pl_directed_link_width : in std_logic_vector(1 downto 0); 00459 pl_upstream_prefer_deemph : in std_logic; 00460 00461 --------------------------------------------------------- 00462 -- 5. System (SYS) Interface 00463 --------------------------------------------------------- 00464 00465 sys_clk : in std_logic; 00466 sys_reset : in std_logic 00467 ); 00468 end cl_v6pcie_x4; 00469 00470 architecture v6_pcie of cl_v6pcie_x4 is 00471 00472 attribute CORE_GENERATION_INFO : string; 00473 attribute CORE_GENERATION_INFO of v6_pcie : ARCHITECTURE is 00474 "cl_v6pcie_x4,v6_pcie_v2_3,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=378,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=FALSE,PIPE_PIPELINE_STAGES=0,REVISION_ID=20,VC_CAP_ON=FALSE}"; 00475 00476 component axi_basic_top 00477 generic ( 00478 C_DATA_WIDTH : integer := 32; -- rx/tx interface data width 00479 C_FAMILY : string := "x7"; -- targeted fpga family 00480 C_ROOT_PORT : BOOLEAN := FALSE; -- pcie block is in root port mode 00481 C_PM_PRIORITY : BOOLEAN := FALSE; -- disable tx packet boundary thrtl 00482 TCQ : integer := 1; -- clock to q time 00483 00484 C_REM_WIDTH : integer := 1; -- trem/rrem width 00485 C_STRB_WIDTH : integer := 4 -- tstrb width 00486 ); 00487 port ( 00488 ----------------------------------------------- 00489 -- user design I/O 00490 ----------------------------------------------- 00491 00492 -- AXI TX 00493 ------------- 00494 s_axis_tx_tdata : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00495 s_axis_tx_tvalid : in std_logic := '0'; 00496 s_axis_tx_tready : out std_logic := '0'; 00497 s_axis_tx_tstrb : in std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0'); 00498 s_axis_tx_tlast : in std_logic := '0'; 00499 s_axis_tx_tuser : in std_logic_vector(3 downto 0) := (others=>'0'); 00500 00501 -- AXI RX 00502 ------------- 00503 m_axis_rx_tdata : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00504 m_axis_rx_tvalid : out std_logic := '0'; 00505 m_axis_rx_tready : in std_logic := '0'; 00506 m_axis_rx_tstrb : out std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0'); 00507 m_axis_rx_tlast : out std_logic := '0'; 00508 m_axis_rx_tuser : out std_logic_vector(21 downto 0) := (others=>'0'); 00509 00510 -- user misc. 00511 ------------- 00512 user_turnoff_ok : in std_logic := '0'; 00513 user_tcfg_gnt : in std_logic := '0'; 00514 00515 ----------------------------------------------- 00516 -- PCIe block I/O 00517 ----------------------------------------------- 00518 00519 -- TRN TX 00520 ------------- 00521 trn_td : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00522 trn_tsof : out std_logic := '0'; 00523 trn_teof : out std_logic := '0'; 00524 trn_tsrc_rdy : out std_logic := '0'; 00525 trn_tdst_rdy : in std_logic := '0'; 00526 trn_tsrc_dsc : out std_logic := '0'; 00527 trn_trem : out std_logic_vector(C_REM_WIDTH - 1 downto 0) := (others=>'0'); 00528 trn_terrfwd : out std_logic := '0'; 00529 trn_tstr : out std_logic := '0'; 00530 trn_tbuf_av : in std_logic_vector(5 downto 0) := (others=>'0'); 00531 trn_tecrc_gen : out std_logic := '0'; 00532 00533 -- TRN RX 00534 ------------- 00535 trn_rd : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00536 trn_rsof : in std_logic := '0'; 00537 trn_reof : in std_logic := '0'; 00538 trn_rsrc_rdy : in std_logic := '0'; 00539 trn_rdst_rdy : out std_logic := '0'; 00540 trn_rsrc_dsc : in std_logic := '0'; 00541 trn_rrem : in std_logic_vector(C_REM_WIDTH - 1 downto 0) := (others=>'0'); 00542 trn_rerrfwd : in std_logic := '0'; 00543 trn_rbar_hit : in std_logic_vector(6 downto 0) := (others=>'0'); 00544 trn_recrc_err : in std_logic := '0'; 00545 00546 -- TRN misc. 00547 ------------- 00548 trn_tcfg_req : in std_logic := '0'; 00549 trn_tcfg_gnt : out std_logic := '0'; 00550 trn_lnk_up : in std_logic := '0'; 00551 00552 -- 7 series/Virtex6 PM 00553 ------------- 00554 cfg_pcie_link_state : in std_logic_vector(2 downto 0) := (others=>'0'); 00555 00556 -- Virtex6 PM 00557 ------------- 00558 cfg_pm_send_pme_to : in std_logic := '0'; 00559 cfg_pmcsr_powerstate : in std_logic_vector(1 downto 0) := (others=>'0'); 00560 trn_rdllp_data : in std_logic_vector(31 downto 0) := (others=>'0'); 00561 trn_rdllp_src_rdy : in std_logic := '0'; 00562 00563 -- Virtex6/Spartan6 PM 00564 ------------- 00565 cfg_to_turnoff : in std_logic := '0'; 00566 cfg_turnoff_ok : out std_logic := '0'; 00567 00568 np_counter : out std_logic_vector(2 downto 0) := (others=>'0'); 00569 user_clk : in std_logic := '0'; 00570 user_rst : in std_logic := '0' 00571 ); 00572 end component; 00573 00574 component pcie_reset_delay_v6 00575 generic ( 00576 PL_FAST_TRAIN : boolean; 00577 REF_CLK_FREQ : integer); 00578 port ( 00579 ref_clk : in std_logic; 00580 sys_reset_n : in std_logic; 00581 delayed_sys_reset_n : out std_logic); 00582 end component; 00583 00584 component pcie_clocking_v6 00585 generic ( 00586 CAP_LINK_WIDTH : integer; 00587 CAP_LINK_SPEED : integer; 00588 REF_CLK_FREQ : integer; 00589 USER_CLK_FREQ : integer); 00590 port ( 00591 sys_clk : in std_logic; 00592 gt_pll_lock : in std_logic; 00593 sel_lnk_rate : in std_logic; 00594 sel_lnk_width : in std_logic_vector(1 downto 0); 00595 sys_clk_bufg : out std_logic; 00596 pipe_clk : out std_logic; 00597 user_clk : out std_logic; 00598 block_clk : out std_logic; 00599 drp_clk : out std_logic; 00600 clock_locked : out std_logic); 00601 end component; 00602 00603 component pcie_2_0_v6 00604 generic ( 00605 REF_CLK_FREQ : integer; 00606 PIPE_PIPELINE_STAGES : integer; 00607 LINK_CAP_MAX_LINK_WIDTH_int : integer; 00608 AER_BASE_PTR : bit_vector; 00609 AER_CAP_ECRC_CHECK_CAPABLE : boolean; 00610 AER_CAP_ECRC_GEN_CAPABLE : boolean; 00611 AER_CAP_ID : bit_vector; 00612 AER_CAP_INT_MSG_NUM_MSI : bit_vector; 00613 AER_CAP_INT_MSG_NUM_MSIX : bit_vector; 00614 AER_CAP_NEXTPTR : bit_vector; 00615 AER_CAP_ON : boolean; 00616 AER_CAP_PERMIT_ROOTERR_UPDATE : boolean; 00617 AER_CAP_VERSION : bit_vector; 00618 ALLOW_X8_GEN2 : boolean; 00619 BAR0 : bit_vector; 00620 BAR1 : bit_vector; 00621 BAR2 : bit_vector; 00622 BAR3 : bit_vector; 00623 BAR4 : bit_vector; 00624 BAR5 : bit_vector; 00625 CAPABILITIES_PTR : bit_vector; 00626 CARDBUS_CIS_POINTER : bit_vector; 00627 CLASS_CODE : bit_vector; 00628 CMD_INTX_IMPLEMENTED : boolean; 00629 CPL_TIMEOUT_DISABLE_SUPPORTED : boolean; 00630 CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector; 00631 CRM_MODULE_RSTS : bit_vector; 00632 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean; 00633 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean; 00634 DEV_CAP_ENDPOINT_L0S_LATENCY : integer; 00635 DEV_CAP_ENDPOINT_L1_LATENCY : integer; 00636 DEV_CAP_EXT_TAG_SUPPORTED : boolean; 00637 DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean; 00638 DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer; 00639 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer; 00640 DEV_CAP_ROLE_BASED_ERROR : boolean; 00641 DEV_CAP_RSVD_14_12 : integer; 00642 DEV_CAP_RSVD_17_16 : integer; 00643 DEV_CAP_RSVD_31_29 : integer; 00644 DEV_CONTROL_AUX_POWER_SUPPORTED : boolean; 00645 DEVICE_ID : bit_vector; 00646 DISABLE_ASPM_L1_TIMER : boolean; 00647 DISABLE_BAR_FILTERING : boolean; 00648 DISABLE_ID_CHECK : boolean; 00649 DISABLE_LANE_REVERSAL : boolean; 00650 DISABLE_RX_TC_FILTER : boolean; 00651 DISABLE_SCRAMBLING : boolean; 00652 DNSTREAM_LINK_NUM : bit_vector; 00653 DSN_BASE_PTR : bit_vector; 00654 DSN_CAP_ID : bit_vector; 00655 DSN_CAP_NEXTPTR : bit_vector; 00656 DSN_CAP_ON : boolean; 00657 DSN_CAP_VERSION : bit_vector; 00658 ENABLE_MSG_ROUTE : bit_vector; 00659 ENABLE_RX_TD_ECRC_TRIM : boolean; 00660 ENTER_RVRY_EI_L0 : boolean; 00661 EXPANSION_ROM : bit_vector; 00662 EXT_CFG_CAP_PTR : bit_vector; 00663 EXT_CFG_XP_CAP_PTR : bit_vector; 00664 HEADER_TYPE : bit_vector; 00665 INFER_EI : bit_vector; 00666 INTERRUPT_PIN : bit_vector; 00667 IS_SWITCH : boolean; 00668 LAST_CONFIG_DWORD : bit_vector; 00669 LINK_CAP_ASPM_SUPPORT : integer; 00670 LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean; 00671 LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean; 00672 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer; 00673 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer; 00674 LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer; 00675 LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer; 00676 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer; 00677 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer; 00678 LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer; 00679 LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer; 00680 LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean; 00681 LINK_CAP_MAX_LINK_SPEED : bit_vector; 00682 LINK_CAP_MAX_LINK_WIDTH : bit_vector; 00683 LINK_CAP_RSVD_23_22 : integer; 00684 LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean; 00685 LINK_CONTROL_RCB : integer; 00686 LINK_CTRL2_DEEMPHASIS : boolean; 00687 LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean; 00688 LINK_CTRL2_TARGET_LINK_SPEED : bit_vector; 00689 LINK_STATUS_SLOT_CLOCK_CONFIG : boolean; 00690 LL_ACK_TIMEOUT : bit_vector; 00691 LL_ACK_TIMEOUT_EN : boolean; 00692 LL_ACK_TIMEOUT_FUNC : integer; 00693 LL_REPLAY_TIMEOUT : bit_vector; 00694 LL_REPLAY_TIMEOUT_EN : boolean; 00695 LL_REPLAY_TIMEOUT_FUNC : integer; 00696 LTSSM_MAX_LINK_WIDTH : bit_vector; 00697 MSI_BASE_PTR : bit_vector; 00698 MSI_CAP_ID : bit_vector; 00699 MSI_CAP_MULTIMSGCAP : integer; 00700 MSI_CAP_MULTIMSG_EXTENSION : integer; 00701 MSI_CAP_NEXTPTR : bit_vector; 00702 MSI_CAP_ON : boolean; 00703 MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean; 00704 MSI_CAP_64_BIT_ADDR_CAPABLE : boolean; 00705 MSIX_BASE_PTR : bit_vector; 00706 MSIX_CAP_ID : bit_vector; 00707 MSIX_CAP_NEXTPTR : bit_vector; 00708 MSIX_CAP_ON : boolean; 00709 MSIX_CAP_PBA_BIR : integer; 00710 MSIX_CAP_PBA_OFFSET : bit_vector; 00711 MSIX_CAP_TABLE_BIR : integer; 00712 MSIX_CAP_TABLE_OFFSET : bit_vector; 00713 MSIX_CAP_TABLE_SIZE : bit_vector; 00714 N_FTS_COMCLK_GEN1 : integer; 00715 N_FTS_COMCLK_GEN2 : integer; 00716 N_FTS_GEN1 : integer; 00717 N_FTS_GEN2 : integer; 00718 PCIE_BASE_PTR : bit_vector; 00719 PCIE_CAP_CAPABILITY_ID : bit_vector; 00720 PCIE_CAP_CAPABILITY_VERSION : bit_vector; 00721 PCIE_CAP_DEVICE_PORT_TYPE : bit_vector; 00722 PCIE_CAP_INT_MSG_NUM : bit_vector; 00723 PCIE_CAP_NEXTPTR : bit_vector; 00724 PCIE_CAP_ON : boolean; 00725 PCIE_CAP_RSVD_15_14 : integer; 00726 PCIE_CAP_SLOT_IMPLEMENTED : boolean; 00727 PCIE_REVISION : integer; 00728 PGL0_LANE : integer; 00729 PGL1_LANE : integer; 00730 PGL2_LANE : integer; 00731 PGL3_LANE : integer; 00732 PGL4_LANE : integer; 00733 PGL5_LANE : integer; 00734 PGL6_LANE : integer; 00735 PGL7_LANE : integer; 00736 PL_AUTO_CONFIG : integer; 00737 PL_FAST_TRAIN : boolean; 00738 PM_BASE_PTR : bit_vector; 00739 PM_CAP_AUXCURRENT : integer; 00740 PM_CAP_DSI : boolean; 00741 PM_CAP_D1SUPPORT : boolean; 00742 PM_CAP_D2SUPPORT : boolean; 00743 PM_CAP_ID : bit_vector; 00744 PM_CAP_NEXTPTR : bit_vector; 00745 PM_CAP_ON : boolean; 00746 PM_CAP_PME_CLOCK : boolean; 00747 PM_CAP_PMESUPPORT : bit_vector; 00748 PM_CAP_RSVD_04 : integer; 00749 PM_CAP_VERSION : integer; 00750 PM_CSR_BPCCEN : boolean; 00751 PM_CSR_B2B3 : boolean; 00752 PM_CSR_NOSOFTRST : boolean; 00753 PM_DATA0 : bit_vector; 00754 PM_DATA1 : bit_vector; 00755 PM_DATA2 : bit_vector; 00756 PM_DATA3 : bit_vector; 00757 PM_DATA4 : bit_vector; 00758 PM_DATA5 : bit_vector; 00759 PM_DATA6 : bit_vector; 00760 PM_DATA7 : bit_vector; 00761 PM_DATA_SCALE0 : bit_vector; 00762 PM_DATA_SCALE1 : bit_vector; 00763 PM_DATA_SCALE2 : bit_vector; 00764 PM_DATA_SCALE3 : bit_vector; 00765 PM_DATA_SCALE4 : bit_vector; 00766 PM_DATA_SCALE5 : bit_vector; 00767 PM_DATA_SCALE6 : bit_vector; 00768 PM_DATA_SCALE7 : bit_vector; 00769 RECRC_CHK : integer; 00770 RECRC_CHK_TRIM : boolean; 00771 REVISION_ID : bit_vector; 00772 ROOT_CAP_CRS_SW_VISIBILITY : boolean; 00773 SELECT_DLL_IF : boolean; 00774 SLOT_CAP_ATT_BUTTON_PRESENT : boolean; 00775 SLOT_CAP_ATT_INDICATOR_PRESENT : boolean; 00776 SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean; 00777 SLOT_CAP_HOTPLUG_CAPABLE : boolean; 00778 SLOT_CAP_HOTPLUG_SURPRISE : boolean; 00779 SLOT_CAP_MRL_SENSOR_PRESENT : boolean; 00780 SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean; 00781 SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector; 00782 SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean; 00783 SLOT_CAP_POWER_INDICATOR_PRESENT : boolean; 00784 SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer; 00785 SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector; 00786 SPARE_BIT0 : integer; 00787 SPARE_BIT1 : integer; 00788 SPARE_BIT2 : integer; 00789 SPARE_BIT3 : integer; 00790 SPARE_BIT4 : integer; 00791 SPARE_BIT5 : integer; 00792 SPARE_BIT6 : integer; 00793 SPARE_BIT7 : integer; 00794 SPARE_BIT8 : integer; 00795 SPARE_BYTE0 : bit_vector; 00796 SPARE_BYTE1 : bit_vector; 00797 SPARE_BYTE2 : bit_vector; 00798 SPARE_BYTE3 : bit_vector; 00799 SPARE_WORD0 : bit_vector; 00800 SPARE_WORD1 : bit_vector; 00801 SPARE_WORD2 : bit_vector; 00802 SPARE_WORD3 : bit_vector; 00803 SUBSYSTEM_ID : bit_vector; 00804 SUBSYSTEM_VENDOR_ID : bit_vector; 00805 TL_RBYPASS : boolean; 00806 TL_RX_RAM_RADDR_LATENCY : integer; 00807 TL_RX_RAM_RDATA_LATENCY : integer; 00808 TL_RX_RAM_WRITE_LATENCY : integer; 00809 TL_TFC_DISABLE : boolean; 00810 TL_TX_CHECKS_DISABLE : boolean; 00811 TL_TX_RAM_RADDR_LATENCY : integer; 00812 TL_TX_RAM_RDATA_LATENCY : integer; 00813 TL_TX_RAM_WRITE_LATENCY : integer; 00814 UPCONFIG_CAPABLE : boolean; 00815 UPSTREAM_FACING : boolean; 00816 UR_INV_REQ : boolean; 00817 USER_CLK_FREQ : integer; 00818 EXIT_LOOPBACK_ON_EI : boolean; 00819 VC_BASE_PTR : bit_vector; 00820 VC_CAP_ID : bit_vector; 00821 VC_CAP_NEXTPTR : bit_vector; 00822 VC_CAP_ON : boolean; 00823 VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean; 00824 VC_CAP_VERSION : bit_vector; 00825 VC0_CPL_INFINITE : boolean; 00826 VC0_RX_RAM_LIMIT : bit_vector; 00827 VC0_TOTAL_CREDITS_CD : integer; 00828 VC0_TOTAL_CREDITS_CH : integer; 00829 VC0_TOTAL_CREDITS_NPH : integer; 00830 VC0_TOTAL_CREDITS_PD : integer; 00831 VC0_TOTAL_CREDITS_PH : integer; 00832 VC0_TX_LASTPACKET : integer; 00833 VENDOR_ID : bit_vector; 00834 VSEC_BASE_PTR : bit_vector; 00835 VSEC_CAP_HDR_ID : bit_vector; 00836 VSEC_CAP_HDR_LENGTH : bit_vector; 00837 VSEC_CAP_HDR_REVISION : bit_vector; 00838 VSEC_CAP_ID : bit_vector; 00839 VSEC_CAP_IS_LINK_VISIBLE : boolean; 00840 VSEC_CAP_NEXTPTR : bit_vector; 00841 VSEC_CAP_ON : boolean; 00842 VSEC_CAP_VERSION : bit_vector); 00843 port ( 00844 PCIEXPRXN : in std_logic_vector(3 downto 0); 00845 PCIEXPRXP : in std_logic_vector(3 downto 0); 00846 PCIEXPTXN : out std_logic_vector(3 downto 0); 00847 PCIEXPTXP : out std_logic_vector(3 downto 0); 00848 SYSCLK : in std_logic; 00849 FUNDRSTN : in std_logic; 00850 TRNLNKUPN : out std_logic; 00851 PHYRDYN : out std_logic; 00852 USERRSTN : out std_logic; 00853 RECEIVEDFUNCLVLRSTN : out std_logic; 00854 LNKCLKEN : out std_logic; 00855 SYSRSTN : in std_logic; 00856 PLRSTN : in std_logic; 00857 DLRSTN : in std_logic; 00858 TLRSTN : in std_logic; 00859 FUNCLVLRSTN : in std_logic; 00860 CMRSTN : in std_logic; 00861 CMSTICKYRSTN : in std_logic; 00862 TRNRBARHITN : out std_logic_vector(6 downto 0); 00863 TRNRD : out std_logic_vector(63 downto 0); 00864 TRNRECRCERRN : out std_logic; 00865 TRNREOFN : out std_logic; 00866 TRNRERRFWDN : out std_logic; 00867 TRNRREMN : out std_logic; 00868 TRNRSOFN : out std_logic; 00869 TRNRSRCDSCN : out std_logic; 00870 TRNRSRCRDYN : out std_logic; 00871 TRNRDSTRDYN : in std_logic; 00872 TRNRNPOKN : in std_logic; 00873 TRNRDLLPDATA : out std_logic_vector(31 downto 0); 00874 TRNRDLLPSRCRDYN : out std_logic; 00875 TRNTBUFAV : out std_logic_vector(5 downto 0); 00876 TRNTCFGREQN : out std_logic; 00877 TRNTDLLPDSTRDYN : out std_logic; 00878 TRNTDSTRDYN : out std_logic; 00879 TRNTERRDROPN : out std_logic; 00880 TRNTCFGGNTN : in std_logic; 00881 TRNTD : in std_logic_vector(63 downto 0); 00882 TRNTDLLPDATA : in std_logic_vector(31 downto 0); 00883 TRNTDLLPSRCRDYN : in std_logic; 00884 TRNTECRCGENN : in std_logic; 00885 TRNTEOFN : in std_logic; 00886 TRNTERRFWDN : in std_logic; 00887 TRNTREMN : in std_logic; 00888 TRNTSOFN : in std_logic; 00889 TRNTSRCDSCN : in std_logic; 00890 TRNTSRCRDYN : in std_logic; 00891 TRNTSTRN : in std_logic; 00892 TRNFCCPLD : out std_logic_vector(11 downto 0); 00893 TRNFCCPLH : out std_logic_vector(7 downto 0); 00894 TRNFCNPD : out std_logic_vector(11 downto 0); 00895 TRNFCNPH : out std_logic_vector(7 downto 0); 00896 TRNFCPD : out std_logic_vector(11 downto 0); 00897 TRNFCPH : out std_logic_vector(7 downto 0); 00898 TRNFCSEL : in std_logic_vector(2 downto 0); 00899 CFGAERECRCCHECKEN : out std_logic; 00900 CFGAERECRCGENEN : out std_logic; 00901 CFGCOMMANDBUSMASTERENABLE : out std_logic; 00902 CFGCOMMANDINTERRUPTDISABLE : out std_logic; 00903 CFGCOMMANDIOENABLE : out std_logic; 00904 CFGCOMMANDMEMENABLE : out std_logic; 00905 CFGCOMMANDSERREN : out std_logic; 00906 CFGDEVCONTROLAUXPOWEREN : out std_logic; 00907 CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic; 00908 CFGDEVCONTROLENABLERO : out std_logic; 00909 CFGDEVCONTROLEXTTAGEN : out std_logic; 00910 CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic; 00911 CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0); 00912 CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0); 00913 CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic; 00914 CFGDEVCONTROLNOSNOOPEN : out std_logic; 00915 CFGDEVCONTROLPHANTOMEN : out std_logic; 00916 CFGDEVCONTROLURERRREPORTINGEN : out std_logic; 00917 CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic; 00918 CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0); 00919 CFGDEVSTATUSCORRERRDETECTED : out std_logic; 00920 CFGDEVSTATUSFATALERRDETECTED : out std_logic; 00921 CFGDEVSTATUSNONFATALERRDETECTED : out std_logic; 00922 CFGDEVSTATUSURDETECTED : out std_logic; 00923 CFGDO : out std_logic_vector(31 downto 0); 00924 CFGERRAERHEADERLOGSETN : out std_logic; 00925 CFGERRCPLRDYN : out std_logic; 00926 CFGINTERRUPTDO : out std_logic_vector(7 downto 0); 00927 CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0); 00928 CFGINTERRUPTMSIENABLE : out std_logic; 00929 CFGINTERRUPTMSIXENABLE : out std_logic; 00930 CFGINTERRUPTMSIXFM : out std_logic; 00931 CFGINTERRUPTRDYN : out std_logic; 00932 CFGLINKCONTROLRCB : out std_logic; 00933 CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0); 00934 CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic; 00935 CFGLINKCONTROLBANDWIDTHINTEN : out std_logic; 00936 CFGLINKCONTROLCLOCKPMEN : out std_logic; 00937 CFGLINKCONTROLCOMMONCLOCK : out std_logic; 00938 CFGLINKCONTROLEXTENDEDSYNC : out std_logic; 00939 CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic; 00940 CFGLINKCONTROLLINKDISABLE : out std_logic; 00941 CFGLINKCONTROLRETRAINLINK : out std_logic; 00942 CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic; 00943 CFGLINKSTATUSBANDWITHSTATUS : out std_logic; 00944 CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0); 00945 CFGLINKSTATUSDLLACTIVE : out std_logic; 00946 CFGLINKSTATUSLINKTRAINING : out std_logic; 00947 CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0); 00948 CFGMSGDATA : out std_logic_vector(15 downto 0); 00949 CFGMSGRECEIVED : out std_logic; 00950 CFGMSGRECEIVEDASSERTINTA : out std_logic; 00951 CFGMSGRECEIVEDASSERTINTB : out std_logic; 00952 CFGMSGRECEIVEDASSERTINTC : out std_logic; 00953 CFGMSGRECEIVEDASSERTINTD : out std_logic; 00954 CFGMSGRECEIVEDDEASSERTINTA : out std_logic; 00955 CFGMSGRECEIVEDDEASSERTINTB : out std_logic; 00956 CFGMSGRECEIVEDDEASSERTINTC : out std_logic; 00957 CFGMSGRECEIVEDDEASSERTINTD : out std_logic; 00958 CFGMSGRECEIVEDERRCOR : out std_logic; 00959 CFGMSGRECEIVEDERRFATAL : out std_logic; 00960 CFGMSGRECEIVEDERRNONFATAL : out std_logic; 00961 CFGMSGRECEIVEDPMASNAK : out std_logic; 00962 CFGMSGRECEIVEDPMETO : out std_logic; 00963 CFGMSGRECEIVEDPMETOACK : out std_logic; 00964 CFGMSGRECEIVEDPMPME : out std_logic; 00965 CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic; 00966 CFGMSGRECEIVEDUNLOCK : out std_logic; 00967 CFGPCIELINKSTATE : out std_logic_vector(2 downto 0); 00968 CFGPMCSRPMEEN : out std_logic; 00969 CFGPMCSRPMESTATUS : out std_logic; 00970 CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0); 00971 CFGPMRCVASREQL1N : out std_logic; 00972 CFGPMRCVENTERL1N : out std_logic; 00973 CFGPMRCVENTERL23N : out std_logic; 00974 CFGPMRCVREQACKN : out std_logic; 00975 CFGRDWRDONEN : out std_logic; 00976 CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic; 00977 CFGTRANSACTION : out std_logic; 00978 CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0); 00979 CFGTRANSACTIONTYPE : out std_logic; 00980 CFGVCTCVCMAP : out std_logic_vector(6 downto 0); 00981 CFGBYTEENN : in std_logic_vector(3 downto 0); 00982 CFGDI : in std_logic_vector(31 downto 0); 00983 CFGDSBUSNUMBER : in std_logic_vector(7 downto 0); 00984 CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0); 00985 CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0); 00986 CFGDSN : in std_logic_vector(63 downto 0); 00987 CFGDWADDR : in std_logic_vector(9 downto 0); 00988 CFGERRACSN : in std_logic; 00989 CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0); 00990 CFGERRCORN : in std_logic; 00991 CFGERRCPLABORTN : in std_logic; 00992 CFGERRCPLTIMEOUTN : in std_logic; 00993 CFGERRCPLUNEXPECTN : in std_logic; 00994 CFGERRECRCN : in std_logic; 00995 CFGERRLOCKEDN : in std_logic; 00996 CFGERRPOSTEDN : in std_logic; 00997 CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0); 00998 CFGERRURN : in std_logic; 00999 CFGINTERRUPTASSERTN : in std_logic; 01000 CFGINTERRUPTDI : in std_logic_vector(7 downto 0); 01001 CFGINTERRUPTN : in std_logic; 01002 CFGPMDIRECTASPML1N : in std_logic; 01003 CFGPMSENDPMACKN : in std_logic; 01004 CFGPMSENDPMETON : in std_logic; 01005 CFGPMSENDPMNAKN : in std_logic; 01006 CFGPMTURNOFFOKN : in std_logic; 01007 CFGPMWAKEN : in std_logic; 01008 CFGPORTNUMBER : in std_logic_vector(7 downto 0); 01009 CFGRDENN : in std_logic; 01010 CFGTRNPENDINGN : in std_logic; 01011 CFGWRENN : in std_logic; 01012 CFGWRREADONLYN : in std_logic; 01013 CFGWRRW1CASRWN : in std_logic; 01014 PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0); 01015 PLLANEREVERSALMODE : out std_logic_vector(1 downto 0); 01016 PLLINKGEN2CAP : out std_logic; 01017 PLLINKPARTNERGEN2SUPPORTED : out std_logic; 01018 PLLINKUPCFGCAP : out std_logic; 01019 PLLTSSMSTATE : out std_logic_vector(5 downto 0); 01020 PLPHYLNKUPN : out std_logic; 01021 PLRECEIVEDHOTRST : out std_logic; 01022 PLRXPMSTATE : out std_logic_vector(1 downto 0); 01023 PLSELLNKRATE : out std_logic; 01024 PLSELLNKWIDTH : out std_logic_vector(1 downto 0); 01025 PLTXPMSTATE : out std_logic_vector(2 downto 0); 01026 PLDIRECTEDLINKAUTON : in std_logic; 01027 PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0); 01028 PLDIRECTEDLINKSPEED : in std_logic; 01029 PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0); 01030 PLDOWNSTREAMDEEMPHSOURCE : in std_logic; 01031 PLUPSTREAMPREFERDEEMPH : in std_logic; 01032 PLTRANSMITHOTRST : in std_logic; 01033 DBGSCLRA : out std_logic; 01034 DBGSCLRB : out std_logic; 01035 DBGSCLRC : out std_logic; 01036 DBGSCLRD : out std_logic; 01037 DBGSCLRE : out std_logic; 01038 DBGSCLRF : out std_logic; 01039 DBGSCLRG : out std_logic; 01040 DBGSCLRH : out std_logic; 01041 DBGSCLRI : out std_logic; 01042 DBGSCLRJ : out std_logic; 01043 DBGSCLRK : out std_logic; 01044 DBGVECA : out std_logic_vector(63 downto 0); 01045 DBGVECB : out std_logic_vector(63 downto 0); 01046 DBGVECC : out std_logic_vector(11 downto 0); 01047 PLDBGVEC : out std_logic_vector(11 downto 0); 01048 DBGMODE : in std_logic_vector(1 downto 0); 01049 DBGSUBMODE : in std_logic; 01050 PLDBGMODE : in std_logic_vector(2 downto 0); 01051 PCIEDRPDO : out std_logic_vector(15 downto 0); 01052 PCIEDRPDRDY : out std_logic; 01053 PCIEDRPCLK : in std_logic; 01054 PCIEDRPDADDR : in std_logic_vector(8 downto 0); 01055 PCIEDRPDEN : in std_logic; 01056 PCIEDRPDI : in std_logic_vector(15 downto 0); 01057 PCIEDRPDWE : in std_logic; 01058 GTPLLLOCK : out std_logic; 01059 PIPECLK : in std_logic; 01060 USERCLK : in std_logic; 01061 DRPCLK : in std_logic; 01062 CLOCKLOCKED : in std_logic; 01063 TxOutClk : out std_logic); 01064 end component; 01065 01066 function to_integer ( 01067 val_in : bit_vector) return integer is 01068 01069 constant vctr : bit_vector(val_in'high-val_in'low downto 0) := val_in; 01070 variable ret : integer := 0; 01071 begin 01072 for index in vctr'range loop 01073 if (vctr(index) = '1') then 01074 ret := ret + (2**index); 01075 end if; 01076 end loop; 01077 return(ret); 01078 end to_integer; 01079 01080 function to_stdlogic ( 01081 in_val : in boolean) return std_logic is 01082 begin 01083 if (in_val) then 01084 return('1'); 01085 else 01086 return('0'); 01087 end if; 01088 end to_stdlogic; 01089 01090 function pad_gen ( 01091 in_vec : bit_vector; 01092 op_len : integer) 01093 return bit_vector is 01094 variable ret : bit_vector(op_len-1 downto 0) := (others => '0'); 01095 constant len : integer := in_vec'length; -- length of input vector 01096 begin -- pad_gen 01097 for i in 0 to op_len-1 loop 01098 if (i < len) then 01099 ret(i) := in_vec(len-i-1); 01100 else 01101 ret(i) := '0'; 01102 end if; 01103 end loop; -- i 01104 return ret; 01105 end pad_gen; 01106 01107 constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED); 01108 01109 signal rx_func_level_reset_n : std_logic; 01110 signal cfg_msg_received : std_logic; 01111 signal cfg_msg_received_pme_to : std_logic; 01112 01113 signal cfg_cmd_bme : std_logic; 01114 signal cfg_cmd_intdis : std_logic; 01115 signal cfg_cmd_io_en : std_logic; 01116 signal cfg_cmd_mem_en : std_logic; 01117 signal cfg_cmd_serr_en : std_logic; 01118 signal cfg_dev_control_aux_power_en : std_logic; 01119 signal cfg_dev_control_corr_err_reporting_en : std_logic; 01120 signal cfg_dev_control_enable_relaxed_order : std_logic; 01121 signal cfg_dev_control_ext_tag_en : std_logic; 01122 signal cfg_dev_control_fatal_err_reporting_en : std_logic; 01123 signal cfg_dev_control_maxpayload : std_logic_vector(2 downto 0); 01124 signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0); 01125 signal cfg_dev_control_non_fatal_reporting_en : std_logic; 01126 signal cfg_dev_control_nosnoop_en : std_logic; 01127 signal cfg_dev_control_phantom_en : std_logic; 01128 signal cfg_dev_control_ur_err_reporting_en : std_logic; 01129 signal cfg_dev_control2_cpltimeout_dis : std_logic; 01130 signal cfg_dev_control2_cpltimeout_val : std_logic_vector(3 downto 0); 01131 signal cfg_dev_status_corr_err_detected : std_logic; 01132 signal cfg_dev_status_fatal_err_detected : std_logic; 01133 signal cfg_dev_status_nonfatal_err_detected : std_logic; 01134 signal cfg_dev_status_ur_detected : std_logic; 01135 signal cfg_link_control_auto_bandwidth_int_en : std_logic; 01136 signal cfg_link_control_bandwidth_int_en : std_logic; 01137 signal cfg_link_control_hw_auto_width_dis : std_logic; 01138 signal cfg_link_control_clock_pm_en : std_logic; 01139 signal cfg_link_control_extended_sync : std_logic; 01140 signal cfg_link_control_common_clock : std_logic; 01141 signal cfg_link_control_retrain_link : std_logic; 01142 signal cfg_link_control_linkdisable : std_logic; 01143 signal cfg_link_control_rcb : std_logic; 01144 signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0); 01145 signal cfg_link_status_autobandwidth_status : std_logic; 01146 signal cfg_link_status_bandwidth_status : std_logic; 01147 signal cfg_link_status_dll_active : std_logic; 01148 signal cfg_link_status_link_training : std_logic; 01149 signal cfg_link_status_negotiated_link_width : std_logic_vector(3 downto 0); 01150 signal cfg_link_status_current_speed : std_logic_vector(1 downto 0); 01151 signal cfg_msg_data : std_logic_vector(15 downto 0); 01152 01153 signal sys_reset_n : std_logic; 01154 signal sys_reset_n_d : std_logic; 01155 signal phy_rdy_n : std_logic; 01156 01157 signal TxOutClk : std_logic; 01158 signal TxOutClk_bufg : std_logic; 01159 01160 signal cfg_bus_number_d : std_logic_vector(7 downto 0); 01161 signal cfg_device_number_d : std_logic_vector(4 downto 0); 01162 signal cfg_function_number_d : std_logic_vector(2 downto 0); 01163 01164 signal trn_rdllp_data : std_logic_vector(31 downto 0); 01165 signal trn_rdllp_src_rdy_n : std_logic; 01166 signal trn_rdllp_src_rdy : std_logic; 01167 01168 -- assigns to outputs 01169 01170 signal gt_pll_lock : std_logic; 01171 01172 signal pipe_clk : std_logic; 01173 signal user_clk : std_logic; 01174 signal clock_locked : std_logic; 01175 signal phy_rdy : std_logic; 01176 01177 signal drp_clk : std_logic; 01178 01179 signal trn_reset_n_d : std_logic; 01180 signal sys_reset_d : std_logic; 01181 signal trn_reset_n : std_logic; 01182 signal trn_reset_n_int1 : std_logic; 01183 signal trn_reset_n_1_d : std_logic; 01184 signal trn_lnk_up_n : std_logic; 01185 signal trn_lnk_up_n_1 : std_logic; 01186 signal user_reset_out_int : std_logic; 01187 signal user_lnk_up_int : std_logic; 01188 signal user_lnk_up_d : std_logic; 01189 signal tx_cfg_req_int : std_logic; 01190 signal cfg_pcie_link_state_int : std_logic_vector(2 downto 0); 01191 signal cfg_pmcsr_powerstate_int : std_logic_vector(1 downto 0); 01192 signal cfg_to_turnoff_int : std_logic; 01193 01194 -- Declare intermediate signals for referenced outputs 01195 signal trn_tcfg_req_n : std_logic; 01196 signal trn_tcfg_gnt_n : std_logic; 01197 signal trn_tcfg_gnt : std_logic; 01198 signal trn_terr_drop_n : std_logic; 01199 signal trn_rdst_rdy_n : std_logic; 01200 signal trn_rnp_ok_n : std_logic; 01201 signal trn_tdst_rdy_n : std_logic; 01202 signal trn_tdst_rdy : std_logic; 01203 signal trn_rd : std_logic_vector(63 downto 0); 01204 signal trn_rrem_n : std_logic; 01205 signal trn_rrem : std_logic_vector(0 downto 0); 01206 signal trn_td : std_logic_vector(63 downto 0); 01207 signal trn_trem_n : std_logic; 01208 signal trn_trem : std_logic_vector(0 downto 0); 01209 signal trn_rsof_n : std_logic; 01210 signal trn_reof_n : std_logic; 01211 signal trn_rsrc_rdy_n : std_logic; 01212 signal trn_rsrc_dsc_n : std_logic; 01213 signal trn_rerrfwd_n : std_logic; 01214 signal trn_rbar_hit_n : std_logic_vector(6 downto 0); 01215 signal trn_recrc_err_n : std_logic; 01216 signal trn_rsof : std_logic; 01217 signal trn_reof : std_logic; 01218 signal trn_rsrc_rdy : std_logic; 01219 signal trn_rdst_rdy : std_logic; 01220 signal trn_rsrc_dsc : std_logic; 01221 signal trn_rerrfwd : std_logic; 01222 signal trn_rbar_hit : std_logic_vector(6 downto 0); 01223 signal trn_recrc_err : std_logic; 01224 signal trn_tsof_n : std_logic; 01225 signal trn_teof_n : std_logic; 01226 signal trn_tsrc_rdy_n : std_logic; 01227 signal trn_tsrc_dsc_n : std_logic; 01228 signal trn_terrfwd_n : std_logic; 01229 signal trn_tstr_n : std_logic; 01230 signal trn_tecrc_gen : std_logic; 01231 signal trn_tsof : std_logic; 01232 signal trn_teof : std_logic; 01233 signal trn_tsrc_rdy : std_logic; 01234 signal trn_tsrc_dsc : std_logic; 01235 signal trn_terrfwd : std_logic; 01236 signal trn_tstr : std_logic; 01237 signal cfg_rd_wr_done_n : std_logic; 01238 signal cfg_err_cpl_rdy_n : std_logic; 01239 signal cfg_interrupt_rdy_n : std_logic; 01240 signal cfg_byte_en_n : std_logic_vector(3 downto 0); 01241 signal cfg_err_cor_n : std_logic; 01242 signal cfg_err_cpl_abort_n : std_logic; 01243 signal cfg_err_cpl_timeout_n : std_logic; 01244 signal cfg_err_cpl_unexpect_n : std_logic; 01245 signal cfg_err_ecrc_n : std_logic; 01246 signal cfg_err_locked_n : std_logic; 01247 signal cfg_err_posted_n : std_logic; 01248 signal cfg_err_ur_n : std_logic; 01249 signal cfg_interrupt_assert_n : std_logic; 01250 signal cfg_interrupt_n : std_logic; 01251 signal cfg_turnoff_ok_n : std_logic; 01252 signal cfg_turnoff_ok_axi : std_logic; 01253 signal cfg_pm_wake_n : std_logic; 01254 signal cfg_rd_en_n : std_logic; 01255 signal cfg_trn_pending_n : std_logic; 01256 signal cfg_wr_en_n : std_logic; 01257 signal tx_buf_av_int : std_logic_vector(5 downto 0); 01258 01259 signal pl_sel_link_rate_int : std_logic; 01260 signal pl_sel_link_width_int : std_logic_vector(1 downto 0); 01261 01262 signal LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus : std_logic; 01263 01264 begin 01265 -- Drive referenced outputs 01266 user_clk_out <= user_clk; 01267 user_reset_out <= user_reset_out_int; 01268 user_lnk_up <= user_lnk_up_int; 01269 pl_sel_link_rate <= pl_sel_link_rate_int; 01270 pl_sel_link_width <= pl_sel_link_width_int; 01271 tx_buf_av <= tx_buf_av_int; 01272 tx_cfg_req_int <= not(trn_tcfg_req_n); 01273 tx_cfg_req <= tx_cfg_req_int; 01274 cfg_pcie_link_state <= cfg_pcie_link_state_int; 01275 cfg_pmcsr_powerstate <= cfg_pmcsr_powerstate_int; 01276 cfg_to_turnoff_int <= cfg_msg_received_pme_to; 01277 cfg_to_turnoff <= cfg_to_turnoff_int; 01278 01279 -- Invert outputs 01280 tx_err_drop <= not(trn_terr_drop_n); 01281 cfg_rd_wr_done <= not(cfg_rd_wr_done_n); 01282 cfg_err_cpl_rdy <= not(cfg_err_cpl_rdy_n); 01283 cfg_interrupt_rdy <= not(cfg_interrupt_rdy_n); 01284 trn_tdst_rdy <= not(trn_tdst_rdy_n); 01285 trn_rsof <= not(trn_rsof_n); 01286 trn_reof <= not(trn_reof_n); 01287 trn_rrem(0) <= not(trn_rrem_n); 01288 trn_rsrc_rdy <= not(trn_rsrc_rdy_n); 01289 trn_rsrc_dsc <= not(trn_rsrc_dsc_n); 01290 trn_rerrfwd <= not(trn_rerrfwd_n); 01291 trn_rbar_hit <= not(trn_rbar_hit_n); 01292 trn_recrc_err <= not(trn_recrc_err_n); 01293 trn_rdllp_src_rdy <= not(trn_rdllp_src_rdy_n); 01294 01295 -- Invert inputs 01296 cfg_byte_en_n <= not(cfg_byte_en); 01297 cfg_err_cor_n <= not(cfg_err_cor); 01298 cfg_err_cpl_abort_n <= not(cfg_err_cpl_abort); 01299 cfg_err_cpl_timeout_n <= not(cfg_err_cpl_timeout); 01300 cfg_err_cpl_unexpect_n <= not(cfg_err_cpl_unexpect); 01301 cfg_err_ecrc_n <= not(cfg_err_ecrc); 01302 cfg_err_locked_n <= not(cfg_err_locked); 01303 cfg_err_posted_n <= not(cfg_err_posted); 01304 cfg_err_ur_n <= not(cfg_err_ur); 01305 cfg_interrupt_assert_n <= not(cfg_interrupt_assert); 01306 cfg_interrupt_n <= not(cfg_interrupt); 01307 cfg_turnoff_ok_n <= not(cfg_turnoff_ok_axi); 01308 cfg_pm_wake_n <= not(cfg_pm_wake); 01309 cfg_rd_en_n <= not(cfg_rd_en); 01310 cfg_trn_pending_n <= not(cfg_trn_pending); 01311 cfg_wr_en_n <= not(cfg_wr_en); 01312 trn_tcfg_gnt_n <= not(trn_tcfg_gnt); 01313 trn_rdst_rdy_n <= not(trn_rdst_rdy); 01314 trn_rnp_ok_n <= not(rx_np_ok); 01315 trn_tsof_n <= not(trn_tsof); 01316 trn_teof_n <= not(trn_teof); 01317 trn_tsrc_rdy_n <= not(trn_tsrc_rdy); 01318 trn_tsrc_dsc_n <= not(trn_tsrc_dsc); 01319 trn_terrfwd_n <= not(trn_terrfwd); 01320 trn_trem_n <= not(trn_trem(0)); 01321 trn_tstr_n <= not(trn_tstr); 01322 01323 LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus <= '1' when (LINK_STATUS_SLOT_CLOCK_CONFIG) else '0'; 01324 01325 -- Calculated/concatenated oututs 01326 cfg_status <= "0000000000000000"; 01327 cfg_command <= ("00000" & 01328 cfg_cmd_intdis & 01329 '0' & 01330 cfg_cmd_serr_en & 01331 "00000" & 01332 cfg_cmd_bme & 01333 cfg_cmd_mem_en & 01334 cfg_cmd_io_en); 01335 cfg_dstatus <= ("0000000000" & 01336 not(cfg_trn_pending_n) & 01337 '0' & 01338 cfg_dev_status_ur_detected & 01339 cfg_dev_status_fatal_err_detected & 01340 cfg_dev_status_nonfatal_err_detected & 01341 cfg_dev_status_corr_err_detected); 01342 cfg_dcommand <= ('0' & 01343 cfg_dev_control_max_read_req & 01344 cfg_dev_control_nosnoop_en & 01345 cfg_dev_control_aux_power_en & 01346 cfg_dev_control_phantom_en & 01347 cfg_dev_control_ext_tag_en & 01348 cfg_dev_control_maxpayload & 01349 cfg_dev_control_enable_relaxed_order & 01350 cfg_dev_control_ur_err_reporting_en & 01351 cfg_dev_control_fatal_err_reporting_en & 01352 cfg_dev_control_non_fatal_reporting_en & 01353 cfg_dev_control_corr_err_reporting_en); 01354 cfg_lstatus <= (cfg_link_status_autobandwidth_status & 01355 cfg_link_status_bandwidth_status & 01356 cfg_link_status_dll_active & 01357 LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus & 01358 cfg_link_status_link_training & 01359 '0' & 01360 "00" & 01361 cfg_link_status_negotiated_link_width & 01362 "00" & 01363 cfg_link_status_current_speed); 01364 cfg_lcommand <= ("0000" & 01365 cfg_link_control_auto_bandwidth_int_en & 01366 cfg_link_control_bandwidth_int_en & 01367 cfg_link_control_hw_auto_width_dis & 01368 cfg_link_control_clock_pm_en & 01369 cfg_link_control_extended_sync & 01370 cfg_link_control_common_clock & 01371 cfg_link_control_retrain_link & 01372 cfg_link_control_linkdisable & 01373 cfg_link_control_rcb & 01374 '0' & 01375 cfg_link_control_aspm_control); 01376 cfg_bus_number <= cfg_bus_number_d; 01377 cfg_device_number <= cfg_device_number_d; 01378 cfg_function_number <= cfg_function_number_d; 01379 cfg_dcommand2 <= ("00000000000" & 01380 cfg_dev_control2_cpltimeout_dis & 01381 cfg_dev_control2_cpltimeout_val); 01382 01383 -- Capture Bus/Device/Function number 01384 01385 process (user_clk) 01386 begin 01387 if (rising_edge(user_clk)) then 01388 if (user_lnk_up_int = '0') then 01389 cfg_bus_number_d <= "00000000"; 01390 cfg_device_number_d <= "00000"; 01391 cfg_function_number_d <= "000"; 01392 elsif (cfg_msg_received = '0') then 01393 cfg_bus_number_d <= cfg_msg_data(15 downto 8); 01394 cfg_device_number_d <= cfg_msg_data(7 downto 3); 01395 cfg_function_number_d <= cfg_msg_data(2 downto 0); 01396 end if; 01397 end if; 01398 end process; 01399 01400 -- Generate user_lnk_up 01401 01402 user_lnk_up_int_i : FDCP 01403 generic map ( 01404 INIT => '0' 01405 ) 01406 port map ( 01407 Q => user_lnk_up_int, 01408 D => user_lnk_up_d, 01409 C => user_clk , 01410 CLR => '0' , 01411 PRE => '0' 01412 ); 01413 01414 user_lnk_up_d <= not(trn_lnk_up_n_1); 01415 01416 trn_lnk_up_n_1_i : FDCP 01417 generic map ( 01418 INIT => '1' 01419 ) 01420 port map ( 01421 Q => trn_lnk_up_n_1, 01422 D => trn_lnk_up_n, 01423 C => user_clk , 01424 CLR => '0' , 01425 PRE => '0' 01426 ); 01427 01428 01429 -- Generate user_reset_out 01430 01431 trn_reset_n_d <= not(trn_reset_n_int1 and not(phy_rdy_n)); 01432 sys_reset_d <= not(sys_reset_n_d); 01433 01434 trn_reset_n_i : FDCP 01435 generic map ( 01436 INIT => '1' 01437 ) 01438 port map ( 01439 Q => user_reset_out_int, 01440 D => trn_reset_n_d, 01441 C => user_clk , 01442 CLR => sys_reset_d , 01443 PRE => '0' 01444 ); 01445 01446 01447 trn_reset_n_1_d <= trn_reset_n and not(phy_rdy_n); 01448 trn_reset_n_int_i : FDCP 01449 generic map ( 01450 INIT => '0' 01451 ) 01452 port map ( 01453 Q => trn_reset_n_int1, 01454 D => trn_reset_n_1_d, 01455 C => user_clk , 01456 CLR => sys_reset_d , 01457 PRE => '0' 01458 ); 01459 01460 01461 --------------------------------------------------------- 01462 -- AXI Basic Bridge 01463 -- Converts between TRN and AXI 01464 --------------------------------------------------------- 01465 01466 axi_basic_top_i : axi_basic_top 01467 generic map ( 01468 C_DATA_WIDTH => 64, -- RX/TX interface data width 01469 C_REM_WIDTH => 1, -- trem/rrem width 01470 C_STRB_WIDTH => 8, -- tstrb width 01471 TCQ => 1, -- Clock to Q time 01472 01473 C_FAMILY => "V6", -- Targeted FPGA family 01474 C_ROOT_PORT => FALSE, -- PCIe block is in root port mode 01475 C_PM_PRIORITY => FALSE -- Disable TX packet boundary thrtl 01476 ) 01477 port map ( 01478 ------------------------------------------------- 01479 -- User Design I/O -- 01480 ------------------------------------------------- 01481 01482 -- AXI TX 01483 ------------- 01484 s_axis_tx_tdata => s_axis_tx_tdata, -- input 01485 s_axis_tx_tvalid => s_axis_tx_tvalid, -- input 01486 s_axis_tx_tready => s_axis_tx_tready, -- output 01487 s_axis_tx_tstrb => s_axis_tx_tstrb, -- input 01488 s_axis_tx_tlast => s_axis_tx_tlast, -- input 01489 s_axis_tx_tuser => s_axis_tx_tuser, -- input 01490 01491 -- AXI RX 01492 ------------- 01493 m_axis_rx_tdata => m_axis_rx_tdata, -- output 01494 m_axis_rx_tvalid => m_axis_rx_tvalid, -- output 01495 m_axis_rx_tready => m_axis_rx_tready, -- input 01496 m_axis_rx_tstrb => m_axis_rx_tstrb, -- output 01497 m_axis_rx_tlast => m_axis_rx_tlast, -- output 01498 m_axis_rx_tuser => m_axis_rx_tuser, -- output 01499 01500 -- User Misc. 01501 ------------- 01502 user_turnoff_ok => cfg_turnoff_ok, -- input 01503 user_tcfg_gnt => tx_cfg_gnt, -- input 01504 01505 ------------------------------------------------- 01506 -- PCIe Block I/O -- 01507 ------------------------------------------------- 01508 01509 -- TRN TX 01510 ------------- 01511 trn_td => trn_td, -- output 01512 trn_tsof => trn_tsof, -- output 01513 trn_teof => trn_teof, -- output 01514 trn_tsrc_rdy => trn_tsrc_rdy, -- output 01515 trn_tdst_rdy => trn_tdst_rdy, -- input 01516 trn_tsrc_dsc => trn_tsrc_dsc, -- output 01517 trn_trem => trn_trem, -- output 01518 trn_terrfwd => trn_terrfwd, -- output 01519 trn_tstr => trn_tstr, -- output 01520 trn_tbuf_av => tx_buf_av_int, -- input 01521 trn_tecrc_gen => trn_tecrc_gen, -- output 01522 01523 -- TRN RX 01524 ------------- 01525 trn_rd => trn_rd, -- input 01526 trn_rsof => trn_rsof, -- input 01527 trn_reof => trn_reof, -- input 01528 trn_rsrc_rdy => trn_rsrc_rdy, -- input 01529 trn_rdst_rdy => trn_rdst_rdy, -- output 01530 trn_rsrc_dsc => trn_rsrc_dsc, -- input 01531 trn_rrem => trn_rrem, -- input 01532 trn_rerrfwd => trn_rerrfwd, -- input 01533 trn_rbar_hit => trn_rbar_hit, -- input 01534 trn_recrc_err => trn_recrc_err, -- input 01535 01536 -- TRN Misc. 01537 ------------- 01538 trn_tcfg_req => tx_cfg_req_int, -- input 01539 trn_tcfg_gnt => trn_tcfg_gnt, -- output 01540 trn_lnk_up => user_lnk_up_int, -- input 01541 01542 -- Artix/Kintex/Virtex PM 01543 ------------- 01544 cfg_pcie_link_state => cfg_pcie_link_state_int, -- input 01545 01546 -- Virtex6 PM 01547 ------------- 01548 cfg_pm_send_pme_to => '0', -- input NOT USED FOR EP 01549 cfg_pmcsr_powerstate => cfg_pmcsr_powerstate_int, -- input 01550 trn_rdllp_data => trn_rdllp_data, -- input 01551 trn_rdllp_src_rdy => trn_rdllp_src_rdy, -- input 01552 01553 -- Power Mgmt for S6/V6 01554 ------------- 01555 cfg_to_turnoff => cfg_to_turnoff_int, -- input 01556 cfg_turnoff_ok => cfg_turnoff_ok_axi, -- output 01557 01558 -- System 01559 ------------- 01560 user_clk => user_clk, -- input 01561 user_rst => user_reset_out_int, -- input 01562 np_counter => open -- output 01563 ); 01564 01565 --------------------------------------------------------- 01566 -- PCI Express Reset Delay Module 01567 --------------------------------------------------------- 01568 01569 sys_reset_n <= not(sys_reset); 01570 01571 pcie_reset_delay_i : pcie_reset_delay_v6 01572 generic map ( 01573 PL_FAST_TRAIN => PL_FAST_TRAIN, 01574 REF_CLK_FREQ => REF_CLK_FREQ 01575 ) 01576 port map ( 01577 ref_clk => TxOutClk_bufg, 01578 sys_reset_n => sys_reset_n, 01579 delayed_sys_reset_n => sys_reset_n_d 01580 ); 01581 01582 01583 --------------------------------------------------------- 01584 -- PCI Express Clocking Module 01585 --------------------------------------------------------- 01586 01587 pcie_clocking_i : pcie_clocking_v6 01588 generic map ( 01589 CAP_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH_int , 01590 CAP_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int , 01591 REF_CLK_FREQ => REF_CLK_FREQ, 01592 USER_CLK_FREQ => USER_CLK_FREQ 01593 ) 01594 port map ( 01595 sys_clk => TxOutClk, 01596 gt_pll_lock => gt_pll_lock, 01597 sel_lnk_rate => pl_sel_link_rate_int, 01598 sel_lnk_width => pl_sel_link_width_int, 01599 sys_clk_bufg => TxOutClk_bufg, 01600 pipe_clk => pipe_clk, 01601 user_clk => user_clk, 01602 block_clk => open, 01603 drp_clk => drp_clk, 01604 clock_locked => clock_locked 01605 ); 01606 01607 01608 phy_rdy <= not(phy_rdy_n); 01609 01610 --------------------------------------------------------- 01611 -- Virtex6 PCI Express Block Module 01612 --------------------------------------------------------- 01613 01614 pcie_2_0_i : pcie_2_0_v6 01615 generic map ( 01616 REF_CLK_FREQ => REF_CLK_FREQ, 01617 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES, 01618 LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int, 01619 AER_BASE_PTR => AER_BASE_PTR, 01620 AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE, 01621 AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE, 01622 AER_CAP_ID => AER_CAP_ID, 01623 AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI, 01624 AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX, 01625 AER_CAP_NEXTPTR => AER_CAP_NEXTPTR, 01626 AER_CAP_ON => AER_CAP_ON, 01627 AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE, 01628 AER_CAP_VERSION => AER_CAP_VERSION, 01629 ALLOW_X8_GEN2 => ALLOW_X8_GEN2, 01630 BAR0 => pad_gen(BAR0, 32), 01631 BAR1 => pad_gen(BAR1, 32), 01632 BAR2 => pad_gen(BAR2, 32), 01633 BAR3 => pad_gen(BAR3, 32), 01634 BAR4 => pad_gen(BAR4, 32), 01635 BAR5 => pad_gen(BAR5, 32), 01636 CAPABILITIES_PTR => CAPABILITIES_PTR, 01637 CARDBUS_CIS_POINTER => pad_gen(CARDBUS_CIS_POINTER, 32), 01638 CLASS_CODE => pad_gen(CLASS_CODE, 24), 01639 CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED, 01640 CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED, 01641 CPL_TIMEOUT_RANGES_SUPPORTED => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4), 01642 CRM_MODULE_RSTS => CRM_MODULE_RSTS, 01643 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE, 01644 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE, 01645 DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY, 01646 DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY, 01647 DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED, 01648 DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE, 01649 DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED, 01650 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT, 01651 DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR, 01652 DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12, 01653 DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16, 01654 DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29, 01655 DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED, 01656 DEVICE_ID => pad_gen(DEVICE_ID, 16), 01657 DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER, 01658 DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING, 01659 DISABLE_ID_CHECK => DISABLE_ID_CHECK, 01660 DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL, 01661 DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER, 01662 DISABLE_SCRAMBLING => DISABLE_SCRAMBLING, 01663 DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM, 01664 DSN_BASE_PTR => pad_gen(DSN_BASE_PTR, 12), 01665 DSN_CAP_ID => DSN_CAP_ID, 01666 DSN_CAP_NEXTPTR => pad_gen(DSN_CAP_NEXTPTR, 12), 01667 DSN_CAP_ON => DSN_CAP_ON, 01668 DSN_CAP_VERSION => DSN_CAP_VERSION, 01669 ENABLE_MSG_ROUTE => pad_gen(ENABLE_MSG_ROUTE, 11), 01670 ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM, 01671 ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0, 01672 EXPANSION_ROM => pad_gen(EXPANSION_ROM, 32), 01673 EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR, 01674 EXT_CFG_XP_CAP_PTR => pad_gen(EXT_CFG_XP_CAP_PTR, 10), 01675 HEADER_TYPE => pad_gen(HEADER_TYPE, 8), 01676 INFER_EI => INFER_EI, 01677 INTERRUPT_PIN => pad_gen(INTERRUPT_PIN, 8), 01678 IS_SWITCH => IS_SWITCH, 01679 LAST_CONFIG_DWORD => LAST_CONFIG_DWORD, 01680 LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT, 01681 LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT, 01682 LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP, 01683 LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP, 01684 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1, 01685 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2, 01686 LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1, 01687 LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2, 01688 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1, 01689 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2, 01690 LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1, 01691 LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2, 01692 LINK_CAP_MAX_LINK_SPEED => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4), 01693 LINK_CAP_MAX_LINK_WIDTH => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6), 01694 LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22, 01695 LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE, 01696 LINK_CONTROL_RCB => LINK_CONTROL_RCB, 01697 LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS, 01698 LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE, 01699 LINK_CTRL2_TARGET_LINK_SPEED => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4), 01700 LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG, 01701 LL_ACK_TIMEOUT => pad_gen(LL_ACK_TIMEOUT, 15), 01702 LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN, 01703 LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC, 01704 LL_REPLAY_TIMEOUT => pad_gen(LL_REPLAY_TIMEOUT, 15), 01705 LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN, 01706 LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC, 01707 LTSSM_MAX_LINK_WIDTH => pad_gen(LTSSM_MAX_LINK_WIDTH, 6), 01708 MSI_BASE_PTR => MSI_BASE_PTR, 01709 MSI_CAP_ID => MSI_CAP_ID, 01710 MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP, 01711 MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION, 01712 MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR, 01713 MSI_CAP_ON => MSI_CAP_ON, 01714 MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE, 01715 MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE, 01716 MSIX_BASE_PTR => MSIX_BASE_PTR, 01717 MSIX_CAP_ID => MSIX_CAP_ID, 01718 MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR, 01719 MSIX_CAP_ON => MSIX_CAP_ON, 01720 MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR, 01721 MSIX_CAP_PBA_OFFSET => pad_gen(MSIX_CAP_PBA_OFFSET, 29), 01722 MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR, 01723 MSIX_CAP_TABLE_OFFSET => pad_gen(MSIX_CAP_TABLE_OFFSET, 29), 01724 MSIX_CAP_TABLE_SIZE => pad_gen(MSIX_CAP_TABLE_SIZE, 11), 01725 N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1, 01726 N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2, 01727 N_FTS_GEN1 => N_FTS_GEN1, 01728 N_FTS_GEN2 => N_FTS_GEN2, 01729 PCIE_BASE_PTR => PCIE_BASE_PTR, 01730 PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID, 01731 PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION, 01732 PCIE_CAP_DEVICE_PORT_TYPE => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4), 01733 PCIE_CAP_INT_MSG_NUM => pad_gen(PCIE_CAP_INT_MSG_NUM, 5), 01734 PCIE_CAP_NEXTPTR => pad_gen(PCIE_CAP_NEXTPTR, 8), 01735 PCIE_CAP_ON => PCIE_CAP_ON, 01736 PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14, 01737 PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED, 01738 PCIE_REVISION => PCIE_REVISION, 01739 PGL0_LANE => PGL0_LANE, 01740 PGL1_LANE => PGL1_LANE, 01741 PGL2_LANE => PGL2_LANE, 01742 PGL3_LANE => PGL3_LANE, 01743 PGL4_LANE => PGL4_LANE, 01744 PGL5_LANE => PGL5_LANE, 01745 PGL6_LANE => PGL6_LANE, 01746 PGL7_LANE => PGL7_LANE, 01747 PL_AUTO_CONFIG => PL_AUTO_CONFIG, 01748 PL_FAST_TRAIN => PL_FAST_TRAIN, 01749 PM_BASE_PTR => PM_BASE_PTR, 01750 PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT, 01751 PM_CAP_DSI => PM_CAP_DSI, 01752 PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT, 01753 PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT, 01754 PM_CAP_ID => PM_CAP_ID, 01755 PM_CAP_NEXTPTR => PM_CAP_NEXTPTR, 01756 PM_CAP_ON => PM_CAP_ON, 01757 PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK, 01758 PM_CAP_PMESUPPORT => pad_gen(PM_CAP_PMESUPPORT, 5), 01759 PM_CAP_RSVD_04 => PM_CAP_RSVD_04, 01760 PM_CAP_VERSION => PM_CAP_VERSION, 01761 PM_CSR_BPCCEN => PM_CSR_BPCCEN, 01762 PM_CSR_B2B3 => PM_CSR_B2B3, 01763 PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST, 01764 PM_DATA_SCALE0 => pad_gen(PM_DATA_SCALE0, 2), 01765 PM_DATA_SCALE1 => pad_gen(PM_DATA_SCALE1, 2), 01766 PM_DATA_SCALE2 => pad_gen(PM_DATA_SCALE2, 2), 01767 PM_DATA_SCALE3 => pad_gen(PM_DATA_SCALE3, 2), 01768 PM_DATA_SCALE4 => pad_gen(PM_DATA_SCALE4, 2), 01769 PM_DATA_SCALE5 => pad_gen(PM_DATA_SCALE5, 2), 01770 PM_DATA_SCALE6 => pad_gen(PM_DATA_SCALE6, 2), 01771 PM_DATA_SCALE7 => pad_gen(PM_DATA_SCALE7, 2), 01772 PM_DATA0 => pad_gen(PM_DATA0, 8), 01773 PM_DATA1 => pad_gen(PM_DATA1, 8), 01774 PM_DATA2 => pad_gen(PM_DATA2, 8), 01775 PM_DATA3 => pad_gen(PM_DATA3, 8), 01776 PM_DATA4 => pad_gen(PM_DATA4, 8), 01777 PM_DATA5 => pad_gen(PM_DATA5, 8), 01778 PM_DATA6 => pad_gen(PM_DATA6, 8), 01779 PM_DATA7 => pad_gen(PM_DATA7, 8), 01780 RECRC_CHK => RECRC_CHK, 01781 RECRC_CHK_TRIM => RECRC_CHK_TRIM, 01782 REVISION_ID => pad_gen(REVISION_ID, 8), 01783 ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY, 01784 SELECT_DLL_IF => SELECT_DLL_IF, 01785 SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT, 01786 SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT, 01787 SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT, 01788 SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE, 01789 SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE, 01790 SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT, 01791 SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT, 01792 SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM, 01793 SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT, 01794 SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT, 01795 SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE, 01796 SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE, 01797 SPARE_BIT0 => SPARE_BIT0, 01798 SPARE_BIT1 => SPARE_BIT1, 01799 SPARE_BIT2 => SPARE_BIT2, 01800 SPARE_BIT3 => SPARE_BIT3, 01801 SPARE_BIT4 => SPARE_BIT4, 01802 SPARE_BIT5 => SPARE_BIT5, 01803 SPARE_BIT6 => SPARE_BIT6, 01804 SPARE_BIT7 => SPARE_BIT7, 01805 SPARE_BIT8 => SPARE_BIT8, 01806 SPARE_BYTE0 => SPARE_BYTE0, 01807 SPARE_BYTE1 => SPARE_BYTE1, 01808 SPARE_BYTE2 => SPARE_BYTE2, 01809 SPARE_BYTE3 => SPARE_BYTE3, 01810 SPARE_WORD0 => SPARE_WORD0, 01811 SPARE_WORD1 => SPARE_WORD1, 01812 SPARE_WORD2 => SPARE_WORD2, 01813 SPARE_WORD3 => SPARE_WORD3, 01814 SUBSYSTEM_ID => pad_gen(SUBSYSTEM_ID, 16), 01815 SUBSYSTEM_VENDOR_ID => pad_gen(SUBSYSTEM_VENDOR_ID, 16), 01816 TL_RBYPASS => TL_RBYPASS, 01817 TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY, 01818 TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY, 01819 TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY, 01820 TL_TFC_DISABLE => TL_TFC_DISABLE, 01821 TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE, 01822 TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY, 01823 TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY, 01824 TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY, 01825 UPCONFIG_CAPABLE => UPCONFIG_CAPABLE, 01826 UPSTREAM_FACING => UPSTREAM_FACING, 01827 EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI, 01828 UR_INV_REQ => UR_INV_REQ, 01829 USER_CLK_FREQ => USER_CLK_FREQ, 01830 VC_BASE_PTR => pad_gen(VC_BASE_PTR, 12), 01831 VC_CAP_ID => VC_CAP_ID, 01832 VC_CAP_NEXTPTR => pad_gen(VC_CAP_NEXTPTR, 12), 01833 VC_CAP_ON => VC_CAP_ON, 01834 VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS, 01835 VC_CAP_VERSION => VC_CAP_VERSION, 01836 VC0_CPL_INFINITE => VC0_CPL_INFINITE, 01837 VC0_RX_RAM_LIMIT => pad_gen(VC0_RX_RAM_LIMIT, 13), 01838 VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD, 01839 VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH, 01840 VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH, 01841 VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD, 01842 VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH, 01843 VC0_TX_LASTPACKET => VC0_TX_LASTPACKET, 01844 VENDOR_ID => pad_gen(VENDOR_ID, 16), 01845 VSEC_BASE_PTR => pad_gen(VSEC_BASE_PTR, 12), 01846 VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID, 01847 VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH, 01848 VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION, 01849 VSEC_CAP_ID => VSEC_CAP_ID, 01850 VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE, 01851 VSEC_CAP_NEXTPTR => pad_gen(VSEC_CAP_NEXTPTR, 12), 01852 VSEC_CAP_ON => VSEC_CAP_ON, 01853 VSEC_CAP_VERSION => VSEC_CAP_VERSION 01854 ) 01855 port map ( 01856 PCIEXPRXN => pci_exp_rxn, 01857 PCIEXPRXP => pci_exp_rxp, 01858 PCIEXPTXN => pci_exp_txn, 01859 PCIEXPTXP => pci_exp_txp, 01860 SYSCLK => sys_clk, 01861 TRNLNKUPN => trn_lnk_up_n, 01862 FUNDRSTN => sys_reset_n_d, 01863 PHYRDYN => phy_rdy_n, 01864 LNKCLKEN => open, 01865 USERRSTN => trn_reset_n, 01866 RECEIVEDFUNCLVLRSTN => rx_func_level_reset_n, 01867 SYSRSTN => phy_rdy, 01868 PLRSTN => '1', 01869 DLRSTN => '1', 01870 TLRSTN => '1', 01871 FUNCLVLRSTN => '1', 01872 CMRSTN => '1', 01873 CMSTICKYRSTN => '1', 01874 01875 TRNRBARHITN => trn_rbar_hit_n, 01876 TRNRD => trn_rd, 01877 TRNRECRCERRN => trn_recrc_err_n, 01878 TRNREOFN => trn_reof_n, 01879 TRNRERRFWDN => trn_rerrfwd_n, 01880 TRNRREMN => trn_rrem_n, 01881 TRNRSOFN => trn_rsof_n, 01882 TRNRSRCDSCN => trn_rsrc_dsc_n, 01883 TRNRSRCRDYN => trn_rsrc_rdy_n, 01884 TRNRDSTRDYN => trn_rdst_rdy_n, 01885 TRNRNPOKN => trn_rnp_ok_n, 01886 TRNRDLLPDATA => trn_rdllp_data, 01887 TRNRDLLPSRCRDYN => trn_rdllp_src_rdy_n, 01888 01889 TRNTBUFAV => tx_buf_av_int, 01890 TRNTCFGREQN => trn_tcfg_req_n, 01891 TRNTDLLPDSTRDYN => open, 01892 TRNTDSTRDYN => trn_tdst_rdy_n, 01893 TRNTERRDROPN => trn_terr_drop_n, 01894 TRNTCFGGNTN => trn_tcfg_gnt_n, 01895 TRNTD => trn_td, 01896 TRNTDLLPDATA => (others => '0'), 01897 TRNTDLLPSRCRDYN => '1', 01898 TRNTECRCGENN => '1', 01899 TRNTEOFN => trn_teof_n, 01900 TRNTERRFWDN => trn_terrfwd_n, 01901 TRNTREMN => trn_trem_n, 01902 TRNTSOFN => trn_tsof_n, 01903 TRNTSRCDSCN => trn_tsrc_dsc_n, 01904 TRNTSRCRDYN => trn_tsrc_rdy_n, 01905 TRNTSTRN => trn_tstr_n, 01906 TRNFCCPLD => fc_cpld, 01907 TRNFCCPLH => fc_cplh, 01908 TRNFCNPD => fc_npd, 01909 TRNFCNPH => fc_nph, 01910 TRNFCPD => fc_pd, 01911 TRNFCPH => fc_ph, 01912 TRNFCSEL => fc_sel, 01913 CFGAERECRCCHECKEN => open, 01914 CFGAERECRCGENEN => open, 01915 CFGCOMMANDBUSMASTERENABLE => cfg_cmd_bme, 01916 CFGCOMMANDINTERRUPTDISABLE => cfg_cmd_intdis, 01917 CFGCOMMANDIOENABLE => cfg_cmd_io_en, 01918 CFGCOMMANDMEMENABLE => cfg_cmd_mem_en, 01919 CFGCOMMANDSERREN => cfg_cmd_serr_en, 01920 CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en, 01921 CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en, 01922 CFGDEVCONTROLENABLERO => cfg_dev_control_enable_relaxed_order, 01923 CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en, 01924 CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en, 01925 CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_maxpayload, 01926 CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req, 01927 CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en, 01928 CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_nosnoop_en, 01929 CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en, 01930 CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en, 01931 CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dev_control2_cpltimeout_dis, 01932 CFGDEVCONTROL2CPLTIMEOUTVAL => cfg_dev_control2_cpltimeout_val, 01933 CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected, 01934 CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected, 01935 CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected, 01936 CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected, 01937 CFGDO => cfg_do, 01938 CFGERRAERHEADERLOGSETN => open , 01939 CFGERRCPLRDYN => cfg_err_cpl_rdy_n, 01940 CFGINTERRUPTDO => cfg_interrupt_do, 01941 CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable, 01942 CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable, 01943 CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable, 01944 CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm, 01945 CFGINTERRUPTRDYN => cfg_interrupt_rdy_n, 01946 CFGLINKCONTROLRCB => cfg_link_control_rcb, 01947 CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control, 01948 CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_link_control_auto_bandwidth_int_en, 01949 CFGLINKCONTROLBANDWIDTHINTEN => cfg_link_control_bandwidth_int_en, 01950 CFGLINKCONTROLCLOCKPMEN => cfg_link_control_clock_pm_en, 01951 CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock, 01952 CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync, 01953 CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_link_control_hw_auto_width_dis, 01954 CFGLINKCONTROLLINKDISABLE => cfg_link_control_linkdisable, 01955 CFGLINKCONTROLRETRAINLINK => cfg_link_control_retrain_link, 01956 CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_link_status_autobandwidth_status, 01957 CFGLINKSTATUSBANDWITHSTATUS => cfg_link_status_bandwidth_status, 01958 CFGLINKSTATUSCURRENTSPEED => cfg_link_status_current_speed, 01959 CFGLINKSTATUSDLLACTIVE => cfg_link_status_dll_active, 01960 CFGLINKSTATUSLINKTRAINING => cfg_link_status_link_training, 01961 CFGLINKSTATUSNEGOTIATEDWIDTH => cfg_link_status_negotiated_link_width, 01962 CFGMSGDATA => cfg_msg_data, 01963 CFGMSGRECEIVED => cfg_msg_received, 01964 CFGMSGRECEIVEDASSERTINTA => open, 01965 CFGMSGRECEIVEDASSERTINTB => open, 01966 CFGMSGRECEIVEDASSERTINTC => open, 01967 CFGMSGRECEIVEDASSERTINTD => open, 01968 CFGMSGRECEIVEDDEASSERTINTA => open, 01969 CFGMSGRECEIVEDDEASSERTINTB => open, 01970 CFGMSGRECEIVEDDEASSERTINTC => open, 01971 CFGMSGRECEIVEDDEASSERTINTD => open, 01972 CFGMSGRECEIVEDERRCOR => open, 01973 CFGMSGRECEIVEDERRFATAL => open, 01974 CFGMSGRECEIVEDERRNONFATAL => open, 01975 CFGMSGRECEIVEDPMASNAK => open, 01976 CFGMSGRECEIVEDPMETO => cfg_msg_received_pme_to, 01977 CFGMSGRECEIVEDPMETOACK => open, 01978 CFGMSGRECEIVEDPMPME => open, 01979 CFGMSGRECEIVEDSETSLOTPOWERLIMIT => open, 01980 CFGMSGRECEIVEDUNLOCK => open, 01981 CFGPCIELINKSTATE => cfg_pcie_link_state_int, 01982 CFGPMCSRPMEEN => cfg_pmcsr_pme_en, 01983 CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status, 01984 CFGPMCSRPOWERSTATE => cfg_pmcsr_powerstate_int, 01985 CFGPMRCVASREQL1N => open, 01986 CFGPMRCVENTERL1N => open, 01987 CFGPMRCVENTERL23N => open, 01988 CFGPMRCVREQACKN => open, 01989 CFGRDWRDONEN => cfg_rd_wr_done_n, 01990 CFGSLOTCONTROLELECTROMECHILCTLPULSE => open, 01991 CFGTRANSACTION => open, 01992 CFGTRANSACTIONADDR => open, 01993 CFGTRANSACTIONTYPE => open, 01994 CFGVCTCVCMAP => open, 01995 CFGBYTEENN => cfg_byte_en_n, 01996 CFGDI => cfg_di, 01997 CFGDSBUSNUMBER => "00000000", 01998 CFGDSDEVICENUMBER => "00000", 01999 CFGDSFUNCTIONNUMBER => "000", 02000 CFGDSN => cfg_dsn, 02001 CFGDWADDR => cfg_dwaddr, 02002 CFGERRACSN => '1', 02003 CFGERRAERHEADERLOG => (others => '0'), 02004 CFGERRCORN => cfg_err_cor_n, 02005 CFGERRCPLABORTN => cfg_err_cpl_abort_n, 02006 CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n, 02007 CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n, 02008 CFGERRECRCN => cfg_err_ecrc_n, 02009 CFGERRLOCKEDN => cfg_err_locked_n, 02010 CFGERRPOSTEDN => cfg_err_posted_n, 02011 CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header, 02012 CFGERRURN => cfg_err_ur_n, 02013 CFGINTERRUPTASSERTN => cfg_interrupt_assert_n, 02014 CFGINTERRUPTDI => cfg_interrupt_di, 02015 CFGINTERRUPTN => cfg_interrupt_n, 02016 CFGPMDIRECTASPML1N => '1', 02017 CFGPMSENDPMACKN => '1', 02018 CFGPMSENDPMETON => '1', 02019 CFGPMSENDPMNAKN => '1', 02020 CFGPMTURNOFFOKN => cfg_turnoff_ok_n, 02021 CFGPMWAKEN => cfg_pm_wake_n, 02022 CFGPORTNUMBER => "00000000", 02023 CFGRDENN => cfg_rd_en_n, 02024 CFGTRNPENDINGN => cfg_trn_pending_n, 02025 CFGWRENN => cfg_wr_en_n, 02026 CFGWRREADONLYN => '1', 02027 CFGWRRW1CASRWN => '1', 02028 02029 PLINITIALLINKWIDTH => pl_initial_link_width, 02030 PLLANEREVERSALMODE => pl_lane_reversal_mode, 02031 PLLINKGEN2CAP => pl_link_gen2_capable, 02032 PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported, 02033 PLLINKUPCFGCAP => pl_link_upcfg_capable, 02034 PLLTSSMSTATE => pl_ltssm_state, 02035 PLPHYLNKUPN => open, -- Debug 02036 PLRECEIVEDHOTRST => pl_received_hot_rst, 02037 PLRXPMSTATE => open, -- Debug 02038 PLSELLNKRATE => pl_sel_link_rate_int, 02039 PLSELLNKWIDTH => pl_sel_link_width_int, 02040 PLTXPMSTATE => open, -- Debug 02041 PLDIRECTEDLINKAUTON => pl_directed_link_auton, 02042 PLDIRECTEDLINKCHANGE => pl_directed_link_change, 02043 PLDIRECTEDLINKSPEED => pl_directed_link_speed, 02044 PLDIRECTEDLINKWIDTH => pl_directed_link_width, 02045 PLDOWNSTREAMDEEMPHSOURCE => '1', 02046 PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph, 02047 PLTRANSMITHOTRST => '0', 02048 02049 DBGSCLRA => open, 02050 DBGSCLRB => open, 02051 DBGSCLRC => open, 02052 DBGSCLRD => open, 02053 DBGSCLRE => open, 02054 DBGSCLRF => open, 02055 DBGSCLRG => open, 02056 DBGSCLRH => open, 02057 DBGSCLRI => open, 02058 DBGSCLRJ => open, 02059 DBGSCLRK => open, 02060 DBGVECA => open, 02061 DBGVECB => open, 02062 DBGVECC => open, 02063 PLDBGVEC => open, 02064 DBGMODE => "00", 02065 DBGSUBMODE => '0', 02066 PLDBGMODE => "000", 02067 02068 PCIEDRPDO => open, 02069 PCIEDRPDRDY => open, 02070 PCIEDRPCLK => '0', 02071 PCIEDRPDADDR => "000000000" , 02072 PCIEDRPDEN => '0', 02073 PCIEDRPDI => X"0000", 02074 PCIEDRPDWE => '0', 02075 02076 GTPLLLOCK => gt_pll_lock , 02077 PIPECLK => pipe_clk, 02078 USERCLK => user_clk, 02079 DRPCLK => drp_clk, 02080 CLOCKLOCKED => clock_locked , 02081 TxOutClk => TxOutClk 02082 ); 02083 02084 end v6_pcie; 02085
1.7.4