|
DS_DMA
|
Signals | |
| reg_ch0_ctrl | std_logic_vector ( 7 downto 0 ) |
| reg_ch1_ctrl | std_logic_vector ( 7 downto 0 ) |
| pf_chn | std_logic |
| ram_adra | std_logic_vector ( 10 downto 0 ) |
| ram_adrb | std_logic_vector ( 10 downto 0 ) |
| ram_we_a | std_logic |
| ram_we_b | std_logic |
| pf_repack_di | std_logic_vector ( 63 downto 0 ) |
| pf_adr | std_logic_vector ( 31 downto 0 ) |
| pf_ram_rd | std_logic |
| pf_ram_rd_z | std_logic |
Component Instantiations | |
| ram1 | ram16x1d |
| ram | RAMB16_S9_S9 |
| cmd | ctrl_ram_cmd <Entity ctrl_ram_cmd> |
См. определение в файле ctrl_ext_ram.vhd строка 137
1.7.4