Граф наследования:pcie_pipe_v6:
Architectures | |
| v6_pcie | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
Generics | |
| NO_OF_LANES | integer := 8 |
| LINK_CAP_MAX_LINK_SPEED | bit_vector := x " 1 " |
| PIPE_PIPELINE_STAGES | integer := 0 |
Ports | |
| pipe_tx_rcvr_det_i | in std_logic |
| pipe_tx_reset_i | in std_logic |
| pipe_tx_rate_i | in std_logic |
| pipe_tx_deemph_i | in std_logic |
| pipe_tx_margin_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_tx_swing_i | in std_logic |
| pipe_tx_rcvr_det_o | out std_logic |
| pipe_tx_reset_o | out std_logic |
| pipe_tx_rate_o | out std_logic |
| pipe_tx_deemph_o | out std_logic |
| pipe_tx_margin_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_tx_swing_o | out std_logic |
| pipe_rx0_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx0_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx0_valid_o | out std_logic |
| pipe_rx0_chanisaligned_o | out std_logic |
| pipe_rx0_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx0_phy_status_o | out std_logic |
| pipe_rx0_elec_idle_o | out std_logic |
| pipe_rx0_polarity_i | in std_logic |
| pipe_tx0_compliance_i | in std_logic |
| pipe_tx0_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx0_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx0_elec_idle_i | in std_logic |
| pipe_tx0_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx0_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx0_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx0_valid_i | in std_logic |
| pipe_rx0_chanisaligned_i | in std_logic |
| pipe_rx0_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx0_phy_status_i | in std_logic |
| pipe_rx0_elec_idle_i | in std_logic |
| pipe_rx0_polarity_o | out std_logic |
| pipe_tx0_compliance_o | out std_logic |
| pipe_tx0_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx0_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx0_elec_idle_o | out std_logic |
| pipe_tx0_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx1_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx1_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx1_valid_o | out std_logic |
| pipe_rx1_chanisaligned_o | out std_logic |
| pipe_rx1_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx1_phy_status_o | out std_logic |
| pipe_rx1_elec_idle_o | out std_logic |
| pipe_rx1_polarity_i | in std_logic |
| pipe_tx1_compliance_i | in std_logic |
| pipe_tx1_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx1_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx1_elec_idle_i | in std_logic |
| pipe_tx1_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx1_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx1_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx1_valid_i | in std_logic |
| pipe_rx1_chanisaligned_i | in std_logic |
| pipe_rx1_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx1_phy_status_i | in std_logic |
| pipe_rx1_elec_idle_i | in std_logic |
| pipe_rx1_polarity_o | out std_logic |
| pipe_tx1_compliance_o | out std_logic |
| pipe_tx1_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx1_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx1_elec_idle_o | out std_logic |
| pipe_tx1_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx2_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx2_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx2_valid_o | out std_logic |
| pipe_rx2_chanisaligned_o | out std_logic |
| pipe_rx2_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx2_phy_status_o | out std_logic |
| pipe_rx2_elec_idle_o | out std_logic |
| pipe_rx2_polarity_i | in std_logic |
| pipe_tx2_compliance_i | in std_logic |
| pipe_tx2_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx2_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx2_elec_idle_i | in std_logic |
| pipe_tx2_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx2_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx2_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx2_valid_i | in std_logic |
| pipe_rx2_chanisaligned_i | in std_logic |
| pipe_rx2_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx2_phy_status_i | in std_logic |
| pipe_rx2_elec_idle_i | in std_logic |
| pipe_rx2_polarity_o | out std_logic |
| pipe_tx2_compliance_o | out std_logic |
| pipe_tx2_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx2_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx2_elec_idle_o | out std_logic |
| pipe_tx2_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx3_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx3_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx3_valid_o | out std_logic |
| pipe_rx3_chanisaligned_o | out std_logic |
| pipe_rx3_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx3_phy_status_o | out std_logic |
| pipe_rx3_elec_idle_o | out std_logic |
| pipe_rx3_polarity_i | in std_logic |
| pipe_tx3_compliance_i | in std_logic |
| pipe_tx3_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx3_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx3_elec_idle_i | in std_logic |
| pipe_tx3_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx3_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx3_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx3_valid_i | in std_logic |
| pipe_rx3_chanisaligned_i | in std_logic |
| pipe_rx3_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx3_phy_status_i | in std_logic |
| pipe_rx3_elec_idle_i | in std_logic |
| pipe_rx3_polarity_o | out std_logic |
| pipe_tx3_compliance_o | out std_logic |
| pipe_tx3_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx3_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx3_elec_idle_o | out std_logic |
| pipe_tx3_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx4_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx4_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx4_valid_o | out std_logic |
| pipe_rx4_chanisaligned_o | out std_logic |
| pipe_rx4_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx4_phy_status_o | out std_logic |
| pipe_rx4_elec_idle_o | out std_logic |
| pipe_rx4_polarity_i | in std_logic |
| pipe_tx4_compliance_i | in std_logic |
| pipe_tx4_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx4_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx4_elec_idle_i | in std_logic |
| pipe_tx4_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx4_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx4_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx4_valid_i | in std_logic |
| pipe_rx4_chanisaligned_i | in std_logic |
| pipe_rx4_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx4_phy_status_i | in std_logic |
| pipe_rx4_elec_idle_i | in std_logic |
| pipe_rx4_polarity_o | out std_logic |
| pipe_tx4_compliance_o | out std_logic |
| pipe_tx4_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx4_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx4_elec_idle_o | out std_logic |
| pipe_tx4_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx5_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx5_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx5_valid_o | out std_logic |
| pipe_rx5_chanisaligned_o | out std_logic |
| pipe_rx5_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx5_phy_status_o | out std_logic |
| pipe_rx5_elec_idle_o | out std_logic |
| pipe_rx5_polarity_i | in std_logic |
| pipe_tx5_compliance_i | in std_logic |
| pipe_tx5_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx5_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx5_elec_idle_i | in std_logic |
| pipe_tx5_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx5_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx5_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx5_valid_i | in std_logic |
| pipe_rx5_chanisaligned_i | in std_logic |
| pipe_rx5_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx5_phy_status_i | in std_logic |
| pipe_rx5_elec_idle_i | in std_logic |
| pipe_rx5_polarity_o | out std_logic |
| pipe_tx5_compliance_o | out std_logic |
| pipe_tx5_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx5_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx5_elec_idle_o | out std_logic |
| pipe_tx5_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx6_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx6_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx6_valid_o | out std_logic |
| pipe_rx6_chanisaligned_o | out std_logic |
| pipe_rx6_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx6_phy_status_o | out std_logic |
| pipe_rx6_elec_idle_o | out std_logic |
| pipe_rx6_polarity_i | in std_logic |
| pipe_tx6_compliance_i | in std_logic |
| pipe_tx6_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx6_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx6_elec_idle_i | in std_logic |
| pipe_tx6_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx6_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx6_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx6_valid_i | in std_logic |
| pipe_rx6_chanisaligned_i | in std_logic |
| pipe_rx6_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx6_phy_status_i | in std_logic |
| pipe_rx6_elec_idle_i | in std_logic |
| pipe_rx6_polarity_o | out std_logic |
| pipe_tx6_compliance_o | out std_logic |
| pipe_tx6_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx6_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx6_elec_idle_o | out std_logic |
| pipe_tx6_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx7_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_rx7_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_rx7_valid_o | out std_logic |
| pipe_rx7_chanisaligned_o | out std_logic |
| pipe_rx7_status_o | out std_logic_vector ( 2 downto 0 ) |
| pipe_rx7_phy_status_o | out std_logic |
| pipe_rx7_elec_idle_o | out std_logic |
| pipe_rx7_polarity_i | in std_logic |
| pipe_tx7_compliance_i | in std_logic |
| pipe_tx7_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_tx7_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_tx7_elec_idle_i | in std_logic |
| pipe_tx7_powerdown_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx7_char_is_k_i | in std_logic_vector ( 1 downto 0 ) |
| pipe_rx7_data_i | in std_logic_vector ( 15 downto 0 ) |
| pipe_rx7_valid_i | in std_logic |
| pipe_rx7_chanisaligned_i | in std_logic |
| pipe_rx7_status_i | in std_logic_vector ( 2 downto 0 ) |
| pipe_rx7_phy_status_i | in std_logic |
| pipe_rx7_elec_idle_i | in std_logic |
| pipe_rx7_polarity_o | out std_logic |
| pipe_tx7_compliance_o | out std_logic |
| pipe_tx7_char_is_k_o | out std_logic_vector ( 1 downto 0 ) |
| pipe_tx7_data_o | out std_logic_vector ( 15 downto 0 ) |
| pipe_tx7_elec_idle_o | out std_logic |
| pipe_tx7_powerdown_o | out std_logic_vector ( 1 downto 0 ) |
| pl_ltssm_state | in std_logic_vector ( 5 downto 0 ) |
| pipe_clk | in std_logic |
| rst_n | in std_logic |
Подробное описание
См. определение в файле pcie_pipe_v6.vhd строка 62
Объявления и описания членов класса находятся в файле:
- pcie_src/pcie_core64_m1/source_virtex6/pcie_pipe_v6.vhd
