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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : pcie_pipe_v6.vhd 00052 -- Version : 2.3 00053 ---- Description: PIPE module for Virtex6 PCIe Block 00054 ---- 00055 ---- 00056 ---- 00057 ---------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 00062 entity pcie_pipe_v6 is 00063 generic ( 00064 NO_OF_LANES : integer := 8; 00065 LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1"; 00066 PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages 00067 ); 00068 port ( 00069 -- Pipe Per-Link Signals 00070 pipe_tx_rcvr_det_i : in std_logic; 00071 pipe_tx_reset_i : in std_logic; 00072 pipe_tx_rate_i : in std_logic; 00073 pipe_tx_deemph_i : in std_logic; 00074 pipe_tx_margin_i : in std_logic_vector(2 downto 0); 00075 pipe_tx_swing_i : in std_logic; 00076 00077 pipe_tx_rcvr_det_o : out std_logic; 00078 pipe_tx_reset_o : out std_logic; 00079 pipe_tx_rate_o : out std_logic; 00080 pipe_tx_deemph_o : out std_logic; 00081 pipe_tx_margin_o : out std_logic_vector(2 downto 0); 00082 pipe_tx_swing_o : out std_logic; 00083 00084 -- Pipe Per-Lane Signals - Lane 0 00085 pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0); 00086 pipe_rx0_data_o : out std_logic_vector(15 downto 0); 00087 pipe_rx0_valid_o : out std_logic; 00088 pipe_rx0_chanisaligned_o : out std_logic; 00089 pipe_rx0_status_o : out std_logic_vector(2 downto 0); 00090 pipe_rx0_phy_status_o : out std_logic; 00091 pipe_rx0_elec_idle_o : out std_logic; 00092 pipe_rx0_polarity_i : in std_logic; 00093 00094 pipe_tx0_compliance_i : in std_logic; 00095 pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0); 00096 pipe_tx0_data_i : in std_logic_vector(15 downto 0); 00097 pipe_tx0_elec_idle_i : in std_logic; 00098 pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0); 00099 00100 pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0); 00101 pipe_rx0_data_i : in std_logic_vector(15 downto 0); 00102 pipe_rx0_valid_i : in std_logic; 00103 pipe_rx0_chanisaligned_i : in std_logic; 00104 pipe_rx0_status_i : in std_logic_vector(2 downto 0); 00105 pipe_rx0_phy_status_i : in std_logic; 00106 pipe_rx0_elec_idle_i : in std_logic; 00107 pipe_rx0_polarity_o : out std_logic; 00108 00109 pipe_tx0_compliance_o : out std_logic; 00110 pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0); 00111 pipe_tx0_data_o : out std_logic_vector(15 downto 0); 00112 pipe_tx0_elec_idle_o : out std_logic; 00113 pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0); 00114 00115 -- Pipe Per-Lane Signals - Lane 1 00116 pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0); 00117 pipe_rx1_data_o : out std_logic_vector(15 downto 0); 00118 pipe_rx1_valid_o : out std_logic; 00119 pipe_rx1_chanisaligned_o : out std_logic; 00120 pipe_rx1_status_o : out std_logic_vector(2 downto 0); 00121 pipe_rx1_phy_status_o : out std_logic; 00122 pipe_rx1_elec_idle_o : out std_logic; 00123 pipe_rx1_polarity_i : in std_logic; 00124 00125 pipe_tx1_compliance_i : in std_logic; 00126 pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0); 00127 pipe_tx1_data_i : in std_logic_vector(15 downto 0); 00128 pipe_tx1_elec_idle_i : in std_logic; 00129 pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0); 00130 00131 pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0); 00132 pipe_rx1_data_i : in std_logic_vector(15 downto 0); 00133 pipe_rx1_valid_i : in std_logic; 00134 pipe_rx1_chanisaligned_i : in std_logic; 00135 pipe_rx1_status_i : in std_logic_vector(2 downto 0); 00136 pipe_rx1_phy_status_i : in std_logic; 00137 pipe_rx1_elec_idle_i : in std_logic; 00138 pipe_rx1_polarity_o : out std_logic; 00139 00140 pipe_tx1_compliance_o : out std_logic; 00141 pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0); 00142 pipe_tx1_data_o : out std_logic_vector(15 downto 0); 00143 pipe_tx1_elec_idle_o : out std_logic; 00144 pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0); 00145 00146 -- Pipe Per-Lane Signals - Lane 2 00147 pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0); 00148 pipe_rx2_data_o : out std_logic_vector(15 downto 0); 00149 pipe_rx2_valid_o : out std_logic; 00150 pipe_rx2_chanisaligned_o : out std_logic; 00151 pipe_rx2_status_o : out std_logic_vector(2 downto 0); 00152 pipe_rx2_phy_status_o : out std_logic; 00153 pipe_rx2_elec_idle_o : out std_logic; 00154 pipe_rx2_polarity_i : in std_logic; 00155 00156 pipe_tx2_compliance_i : in std_logic; 00157 pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0); 00158 pipe_tx2_data_i : in std_logic_vector(15 downto 0); 00159 pipe_tx2_elec_idle_i : in std_logic; 00160 pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0); 00161 00162 pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0); 00163 pipe_rx2_data_i : in std_logic_vector(15 downto 0); 00164 pipe_rx2_valid_i : in std_logic; 00165 pipe_rx2_chanisaligned_i : in std_logic; 00166 pipe_rx2_status_i : in std_logic_vector(2 downto 0); 00167 pipe_rx2_phy_status_i : in std_logic; 00168 pipe_rx2_elec_idle_i : in std_logic; 00169 pipe_rx2_polarity_o : out std_logic; 00170 00171 pipe_tx2_compliance_o : out std_logic; 00172 pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0); 00173 pipe_tx2_data_o : out std_logic_vector(15 downto 0); 00174 pipe_tx2_elec_idle_o : out std_logic; 00175 pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0); 00176 00177 -- Pipe Per-Lane Signals - Lane 3 00178 pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0); 00179 pipe_rx3_data_o : out std_logic_vector(15 downto 0); 00180 pipe_rx3_valid_o : out std_logic; 00181 pipe_rx3_chanisaligned_o : out std_logic; 00182 pipe_rx3_status_o : out std_logic_vector(2 downto 0); 00183 pipe_rx3_phy_status_o : out std_logic; 00184 pipe_rx3_elec_idle_o : out std_logic; 00185 pipe_rx3_polarity_i : in std_logic; 00186 00187 pipe_tx3_compliance_i : in std_logic; 00188 pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0); 00189 pipe_tx3_data_i : in std_logic_vector(15 downto 0); 00190 pipe_tx3_elec_idle_i : in std_logic; 00191 pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0); 00192 00193 pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0); 00194 pipe_rx3_data_i : in std_logic_vector(15 downto 0); 00195 pipe_rx3_valid_i : in std_logic; 00196 pipe_rx3_chanisaligned_i : in std_logic; 00197 pipe_rx3_status_i : in std_logic_vector(2 downto 0); 00198 pipe_rx3_phy_status_i : in std_logic; 00199 pipe_rx3_elec_idle_i : in std_logic; 00200 pipe_rx3_polarity_o : out std_logic; 00201 00202 pipe_tx3_compliance_o : out std_logic; 00203 pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0); 00204 pipe_tx3_data_o : out std_logic_vector(15 downto 0); 00205 pipe_tx3_elec_idle_o : out std_logic; 00206 pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0); 00207 00208 -- Pipe Per-Lane Signals - Lane 4 00209 pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0); 00210 pipe_rx4_data_o : out std_logic_vector(15 downto 0); 00211 pipe_rx4_valid_o : out std_logic; 00212 pipe_rx4_chanisaligned_o : out std_logic; 00213 pipe_rx4_status_o : out std_logic_vector(2 downto 0); 00214 pipe_rx4_phy_status_o : out std_logic; 00215 pipe_rx4_elec_idle_o : out std_logic; 00216 pipe_rx4_polarity_i : in std_logic; 00217 00218 pipe_tx4_compliance_i : in std_logic; 00219 pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0); 00220 pipe_tx4_data_i : in std_logic_vector(15 downto 0); 00221 pipe_tx4_elec_idle_i : in std_logic; 00222 pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0); 00223 00224 pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0); 00225 pipe_rx4_data_i : in std_logic_vector(15 downto 0); 00226 pipe_rx4_valid_i : in std_logic; 00227 pipe_rx4_chanisaligned_i : in std_logic; 00228 pipe_rx4_status_i : in std_logic_vector(2 downto 0); 00229 pipe_rx4_phy_status_i : in std_logic; 00230 pipe_rx4_elec_idle_i : in std_logic; 00231 pipe_rx4_polarity_o : out std_logic; 00232 00233 pipe_tx4_compliance_o : out std_logic; 00234 pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0); 00235 pipe_tx4_data_o : out std_logic_vector(15 downto 0); 00236 pipe_tx4_elec_idle_o : out std_logic; 00237 pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0); 00238 00239 -- Pipe Per-Lane Signals - Lane 5 00240 pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0); 00241 pipe_rx5_data_o : out std_logic_vector(15 downto 0); 00242 pipe_rx5_valid_o : out std_logic; 00243 pipe_rx5_chanisaligned_o : out std_logic; 00244 pipe_rx5_status_o : out std_logic_vector(2 downto 0); 00245 pipe_rx5_phy_status_o : out std_logic; 00246 pipe_rx5_elec_idle_o : out std_logic; 00247 pipe_rx5_polarity_i : in std_logic; 00248 00249 pipe_tx5_compliance_i : in std_logic; 00250 pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0); 00251 pipe_tx5_data_i : in std_logic_vector(15 downto 0); 00252 pipe_tx5_elec_idle_i : in std_logic; 00253 pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0); 00254 00255 pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0); 00256 pipe_rx5_data_i : in std_logic_vector(15 downto 0); 00257 pipe_rx5_valid_i : in std_logic; 00258 pipe_rx5_chanisaligned_i : in std_logic; 00259 pipe_rx5_status_i : in std_logic_vector(2 downto 0); 00260 pipe_rx5_phy_status_i : in std_logic; 00261 pipe_rx5_elec_idle_i : in std_logic; 00262 pipe_rx5_polarity_o : out std_logic; 00263 00264 pipe_tx5_compliance_o : out std_logic; 00265 pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0); 00266 pipe_tx5_data_o : out std_logic_vector(15 downto 0); 00267 pipe_tx5_elec_idle_o : out std_logic; 00268 pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0); 00269 00270 -- Pipe Per-Lane Signals - Lane 6 00271 pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0); 00272 pipe_rx6_data_o : out std_logic_vector(15 downto 0); 00273 pipe_rx6_valid_o : out std_logic; 00274 pipe_rx6_chanisaligned_o : out std_logic; 00275 pipe_rx6_status_o : out std_logic_vector(2 downto 0); 00276 pipe_rx6_phy_status_o : out std_logic; 00277 pipe_rx6_elec_idle_o : out std_logic; 00278 pipe_rx6_polarity_i : in std_logic; 00279 00280 pipe_tx6_compliance_i : in std_logic; 00281 pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0); 00282 pipe_tx6_data_i : in std_logic_vector(15 downto 0); 00283 pipe_tx6_elec_idle_i : in std_logic; 00284 pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0); 00285 00286 pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0); 00287 pipe_rx6_data_i : in std_logic_vector(15 downto 0); 00288 pipe_rx6_valid_i : in std_logic; 00289 pipe_rx6_chanisaligned_i : in std_logic; 00290 pipe_rx6_status_i : in std_logic_vector(2 downto 0); 00291 pipe_rx6_phy_status_i : in std_logic; 00292 pipe_rx6_elec_idle_i : in std_logic; 00293 pipe_rx6_polarity_o : out std_logic; 00294 00295 pipe_tx6_compliance_o : out std_logic; 00296 pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0); 00297 pipe_tx6_data_o : out std_logic_vector(15 downto 0); 00298 pipe_tx6_elec_idle_o : out std_logic; 00299 pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0); 00300 00301 -- Pipe Per-Lane Signals - Lane 7 00302 pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0); 00303 pipe_rx7_data_o : out std_logic_vector(15 downto 0); 00304 pipe_rx7_valid_o : out std_logic; 00305 pipe_rx7_chanisaligned_o : out std_logic; 00306 pipe_rx7_status_o : out std_logic_vector(2 downto 0); 00307 pipe_rx7_phy_status_o : out std_logic; 00308 pipe_rx7_elec_idle_o : out std_logic; 00309 pipe_rx7_polarity_i : in std_logic; 00310 00311 pipe_tx7_compliance_i : in std_logic; 00312 pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0); 00313 pipe_tx7_data_i : in std_logic_vector(15 downto 0); 00314 pipe_tx7_elec_idle_i : in std_logic; 00315 pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0); 00316 00317 pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0); 00318 pipe_rx7_data_i : in std_logic_vector(15 downto 0); 00319 pipe_rx7_valid_i : in std_logic; 00320 pipe_rx7_chanisaligned_i : in std_logic; 00321 pipe_rx7_status_i : in std_logic_vector(2 downto 0); 00322 pipe_rx7_phy_status_i : in std_logic; 00323 pipe_rx7_elec_idle_i : in std_logic; 00324 pipe_rx7_polarity_o : out std_logic; 00325 00326 pipe_tx7_compliance_o : out std_logic; 00327 pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0); 00328 pipe_tx7_data_o : out std_logic_vector(15 downto 0); 00329 pipe_tx7_elec_idle_o : out std_logic; 00330 pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0); 00331 00332 -- Non PIPE signals 00333 pl_ltssm_state : in std_logic_vector(5 downto 0); 00334 pipe_clk : in std_logic; 00335 rst_n : in std_logic 00336 ); 00337 end pcie_pipe_v6; 00338 00339 architecture v6_pcie of pcie_pipe_v6 is 00340 component pcie_pipe_lane_v6 is 00341 generic ( 00342 PIPE_PIPELINE_STAGES : integer := 0 00343 ); 00344 port ( 00345 pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0); 00346 pipe_rx_data_o : out std_logic_vector(15 downto 0); 00347 pipe_rx_valid_o : out std_logic; 00348 pipe_rx_chanisaligned_o : out std_logic; 00349 pipe_rx_status_o : out std_logic_vector(2 downto 0); 00350 pipe_rx_phy_status_o : out std_logic; 00351 pipe_rx_elec_idle_o : out std_logic; 00352 pipe_rx_polarity_i : in std_logic; 00353 pipe_tx_compliance_i : in std_logic; 00354 pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0); 00355 pipe_tx_data_i : in std_logic_vector(15 downto 0); 00356 pipe_tx_elec_idle_i : in std_logic; 00357 pipe_tx_powerdown_i : in std_logic_vector(1 downto 0); 00358 pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0); 00359 pipe_rx_data_i : in std_logic_vector(15 downto 0); 00360 pipe_rx_valid_i : in std_logic; 00361 pipe_rx_chanisaligned_i : in std_logic; 00362 pipe_rx_status_i : in std_logic_vector(2 downto 0); 00363 pipe_rx_phy_status_i : in std_logic; 00364 pipe_rx_elec_idle_i : in std_logic; 00365 pipe_rx_polarity_o : out std_logic; 00366 pipe_tx_compliance_o : out std_logic; 00367 pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0); 00368 pipe_tx_data_o : out std_logic_vector(15 downto 0); 00369 pipe_tx_elec_idle_o : out std_logic; 00370 pipe_tx_powerdown_o : out std_logic_vector(1 downto 0); 00371 pipe_clk : in std_logic; 00372 rst_n : in std_logic 00373 ); 00374 end component; 00375 00376 component pcie_pipe_misc_v6 is 00377 generic ( 00378 PIPE_PIPELINE_STAGES : integer := 0 00379 ); 00380 port ( 00381 pipe_tx_rcvr_det_i : in std_logic; 00382 pipe_tx_reset_i : in std_logic; 00383 pipe_tx_rate_i : in std_logic; 00384 pipe_tx_deemph_i : in std_logic; 00385 pipe_tx_margin_i : in std_logic_vector(2 downto 0); 00386 pipe_tx_swing_i : in std_logic; 00387 pipe_tx_rcvr_det_o : out std_logic; 00388 pipe_tx_reset_o : out std_logic; 00389 pipe_tx_rate_o : out std_logic; 00390 pipe_tx_deemph_o : out std_logic; 00391 pipe_tx_margin_o : out std_logic_vector(2 downto 0); 00392 pipe_tx_swing_o : out std_logic; 00393 pipe_clk : in std_logic; 00394 rst_n : in std_logic 00395 ); 00396 end component; 00397 00398 --******************************************************************// 00399 -- Reality check. // 00400 --******************************************************************// 00401 00402 constant Tc2o : integer := 1; -- clock to out delay model 00403 00404 signal pipe_rx0_char_is_k_q : std_logic_vector(1 downto 0); 00405 signal pipe_rx0_data_q : std_logic_vector(15 downto 0); 00406 signal pipe_rx1_char_is_k_q : std_logic_vector(1 downto 0); 00407 signal pipe_rx1_data_q : std_logic_vector(15 downto 0); 00408 signal pipe_rx2_char_is_k_q : std_logic_vector(1 downto 0); 00409 signal pipe_rx2_data_q : std_logic_vector(15 downto 0); 00410 signal pipe_rx3_char_is_k_q : std_logic_vector(1 downto 0); 00411 signal pipe_rx3_data_q : std_logic_vector(15 downto 0); 00412 signal pipe_rx4_char_is_k_q : std_logic_vector(1 downto 0); 00413 signal pipe_rx4_data_q : std_logic_vector(15 downto 0); 00414 signal pipe_rx5_char_is_k_q : std_logic_vector(1 downto 0); 00415 signal pipe_rx5_data_q : std_logic_vector(15 downto 0); 00416 signal pipe_rx6_char_is_k_q : std_logic_vector(1 downto 0); 00417 signal pipe_rx6_data_q : std_logic_vector(15 downto 0); 00418 signal pipe_rx7_char_is_k_q : std_logic_vector(1 downto 0); 00419 signal pipe_rx7_data_q : std_logic_vector(15 downto 0); 00420 00421 -- Declare intermediate signals for referenced outputs 00422 signal pipe_tx_rcvr_det_o_v6pcie91 : std_logic; 00423 signal pipe_tx_reset_o_v6pcie92 : std_logic; 00424 signal pipe_tx_rate_o_v6pcie90 : std_logic; 00425 signal pipe_tx_deemph_o_v6pcie88 : std_logic; 00426 signal pipe_tx_margin_o_v6pcie89 : std_logic_vector(2 downto 0); 00427 signal pipe_tx_swing_o_v6pcie93 : std_logic; 00428 signal pipe_rx0_valid_o_v6pcie5 : std_logic; 00429 signal pipe_rx0_chanisaligned_o_v6pcie0 : std_logic; 00430 signal pipe_rx0_status_o_v6pcie4 : std_logic_vector(2 downto 0); 00431 signal pipe_rx0_phy_status_o_v6pcie2 : std_logic; 00432 signal pipe_rx0_elec_idle_o_v6pcie1 : std_logic; 00433 signal pipe_rx0_polarity_o_v6pcie3 : std_logic; 00434 signal pipe_tx0_compliance_o_v6pcie49 : std_logic; 00435 signal pipe_tx0_char_is_k_o_v6pcie48 : std_logic_vector(1 downto 0); 00436 signal pipe_tx0_data_o_v6pcie50 : std_logic_vector(15 downto 0); 00437 signal pipe_tx0_elec_idle_o_v6pcie51 : std_logic; 00438 signal pipe_tx0_powerdown_o_v6pcie52 : std_logic_vector(1 downto 0); 00439 signal pipe_rx1_valid_o_v6pcie11 : std_logic; 00440 signal pipe_rx1_chanisaligned_o_v6pcie6 : std_logic; 00441 signal pipe_rx1_status_o_v6pcie10 : std_logic_vector(2 downto 0); 00442 signal pipe_rx1_phy_status_o_v6pcie8 : std_logic; 00443 signal pipe_rx1_elec_idle_o_v6pcie7 : std_logic; 00444 signal pipe_rx1_polarity_o_v6pcie9 : std_logic; 00445 signal pipe_tx1_compliance_o_v6pcie54 : std_logic; 00446 signal pipe_tx1_char_is_k_o_v6pcie53 : std_logic_vector(1 downto 0); 00447 signal pipe_tx1_data_o_v6pcie55 : std_logic_vector(15 downto 0); 00448 signal pipe_tx1_elec_idle_o_v6pcie56 : std_logic; 00449 signal pipe_tx1_powerdown_o_v6pcie57 : std_logic_vector(1 downto 0); 00450 signal pipe_rx2_valid_o_v6pcie17 : std_logic; 00451 signal pipe_rx2_chanisaligned_o_v6pcie12 : std_logic; 00452 signal pipe_rx2_status_o_v6pcie16 : std_logic_vector(2 downto 0); 00453 signal pipe_rx2_phy_status_o_v6pcie14 : std_logic; 00454 signal pipe_rx2_elec_idle_o_v6pcie13 : std_logic; 00455 signal pipe_rx2_polarity_o_v6pcie15 : std_logic; 00456 signal pipe_tx2_compliance_o_v6pcie59 : std_logic; 00457 signal pipe_tx2_char_is_k_o_v6pcie58 : std_logic_vector(1 downto 0); 00458 signal pipe_tx2_data_o_v6pcie60 : std_logic_vector(15 downto 0); 00459 signal pipe_tx2_elec_idle_o_v6pcie61 : std_logic; 00460 signal pipe_tx2_powerdown_o_v6pcie62 : std_logic_vector(1 downto 0); 00461 signal pipe_rx3_valid_o_v6pcie23 : std_logic; 00462 signal pipe_rx3_chanisaligned_o_v6pcie18 : std_logic; 00463 signal pipe_rx3_status_o_v6pcie22 : std_logic_vector(2 downto 0); 00464 signal pipe_rx3_phy_status_o_v6pcie20 : std_logic; 00465 signal pipe_rx3_elec_idle_o_v6pcie19 : std_logic; 00466 signal pipe_rx3_polarity_o_v6pcie21 : std_logic; 00467 signal pipe_tx3_compliance_o_v6pcie64 : std_logic; 00468 signal pipe_tx3_char_is_k_o_v6pcie63 : std_logic_vector(1 downto 0); 00469 signal pipe_tx3_data_o_v6pcie65 : std_logic_vector(15 downto 0); 00470 signal pipe_tx3_elec_idle_o_v6pcie66 : std_logic; 00471 signal pipe_tx3_powerdown_o_v6pcie67 : std_logic_vector(1 downto 0); 00472 signal pipe_rx4_valid_o_v6pcie29 : std_logic; 00473 signal pipe_rx4_chanisaligned_o_v6pcie24 : std_logic; 00474 signal pipe_rx4_status_o_v6pcie28 : std_logic_vector(2 downto 0); 00475 signal pipe_rx4_phy_status_o_v6pcie26 : std_logic; 00476 signal pipe_rx4_elec_idle_o_v6pcie25 : std_logic; 00477 signal pipe_rx4_polarity_o_v6pcie27 : std_logic; 00478 signal pipe_tx4_compliance_o_v6pcie69 : std_logic; 00479 signal pipe_tx4_char_is_k_o_v6pcie68 : std_logic_vector(1 downto 0); 00480 signal pipe_tx4_data_o_v6pcie70 : std_logic_vector(15 downto 0); 00481 signal pipe_tx4_elec_idle_o_v6pcie71 : std_logic; 00482 signal pipe_tx4_powerdown_o_v6pcie72 : std_logic_vector(1 downto 0); 00483 signal pipe_rx5_valid_o_v6pcie35 : std_logic; 00484 signal pipe_rx5_chanisaligned_o_v6pcie30 : std_logic; 00485 signal pipe_rx5_status_o_v6pcie34 : std_logic_vector(2 downto 0); 00486 signal pipe_rx5_phy_status_o_v6pcie32 : std_logic; 00487 signal pipe_rx5_elec_idle_o_v6pcie31 : std_logic; 00488 signal pipe_rx5_polarity_o_v6pcie33 : std_logic; 00489 signal pipe_tx5_compliance_o_v6pcie74 : std_logic; 00490 signal pipe_tx5_char_is_k_o_v6pcie73 : std_logic_vector(1 downto 0); 00491 signal pipe_tx5_data_o_v6pcie75 : std_logic_vector(15 downto 0); 00492 signal pipe_tx5_elec_idle_o_v6pcie76 : std_logic; 00493 signal pipe_tx5_powerdown_o_v6pcie77 : std_logic_vector(1 downto 0); 00494 signal pipe_rx6_valid_o_v6pcie41 : std_logic; 00495 signal pipe_rx6_chanisaligned_o_v6pcie36 : std_logic; 00496 signal pipe_rx6_status_o_v6pcie40 : std_logic_vector(2 downto 0); 00497 signal pipe_rx6_phy_status_o_v6pcie38 : std_logic; 00498 signal pipe_rx6_elec_idle_o_v6pcie37 : std_logic; 00499 signal pipe_rx6_polarity_o_v6pcie39 : std_logic; 00500 signal pipe_tx6_compliance_o_v6pcie79 : std_logic; 00501 signal pipe_tx6_char_is_k_o_v6pcie78 : std_logic_vector(1 downto 0); 00502 signal pipe_tx6_data_o_v6pcie80 : std_logic_vector(15 downto 0); 00503 signal pipe_tx6_elec_idle_o_v6pcie81 : std_logic; 00504 signal pipe_tx6_powerdown_o_v6pcie82 : std_logic_vector(1 downto 0); 00505 signal pipe_rx7_valid_o_v6pcie47 : std_logic; 00506 signal pipe_rx7_chanisaligned_o_v6pcie42 : std_logic; 00507 signal pipe_rx7_status_o_v6pcie46 : std_logic_vector(2 downto 0); 00508 signal pipe_rx7_phy_status_o_v6pcie44 : std_logic; 00509 signal pipe_rx7_elec_idle_o_v6pcie43 : std_logic; 00510 signal pipe_rx7_polarity_o_v6pcie45 : std_logic; 00511 signal pipe_tx7_compliance_o_v6pcie84 : std_logic; 00512 signal pipe_tx7_char_is_k_o_v6pcie83 : std_logic_vector(1 downto 0); 00513 signal pipe_tx7_data_o_v6pcie85 : std_logic_vector(15 downto 0); 00514 signal pipe_tx7_elec_idle_o_v6pcie86 : std_logic; 00515 signal pipe_tx7_powerdown_o_v6pcie87 : std_logic_vector(1 downto 0); 00516 begin 00517 -- Drive referenced outputs 00518 pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_o_v6pcie91; 00519 pipe_tx_reset_o <= pipe_tx_reset_o_v6pcie92; 00520 pipe_tx_rate_o <= pipe_tx_rate_o_v6pcie90; 00521 pipe_tx_deemph_o <= pipe_tx_deemph_o_v6pcie88; 00522 pipe_tx_margin_o <= pipe_tx_margin_o_v6pcie89; 00523 pipe_tx_swing_o <= pipe_tx_swing_o_v6pcie93; 00524 pipe_rx0_valid_o <= pipe_rx0_valid_o_v6pcie5; 00525 pipe_rx0_chanisaligned_o <= pipe_rx0_chanisaligned_o_v6pcie0; 00526 pipe_rx0_status_o <= pipe_rx0_status_o_v6pcie4; 00527 pipe_rx0_phy_status_o <= pipe_rx0_phy_status_o_v6pcie2; 00528 pipe_rx0_elec_idle_o <= pipe_rx0_elec_idle_o_v6pcie1; 00529 pipe_rx0_polarity_o <= pipe_rx0_polarity_o_v6pcie3; 00530 pipe_tx0_compliance_o <= pipe_tx0_compliance_o_v6pcie49; 00531 pipe_tx0_char_is_k_o <= pipe_tx0_char_is_k_o_v6pcie48; 00532 pipe_tx0_data_o <= pipe_tx0_data_o_v6pcie50; 00533 pipe_tx0_elec_idle_o <= pipe_tx0_elec_idle_o_v6pcie51; 00534 pipe_tx0_powerdown_o <= pipe_tx0_powerdown_o_v6pcie52; 00535 pipe_rx1_valid_o <= pipe_rx1_valid_o_v6pcie11; 00536 pipe_rx1_chanisaligned_o <= pipe_rx1_chanisaligned_o_v6pcie6; 00537 pipe_rx1_status_o <= pipe_rx1_status_o_v6pcie10; 00538 pipe_rx1_phy_status_o <= pipe_rx1_phy_status_o_v6pcie8; 00539 pipe_rx1_elec_idle_o <= pipe_rx1_elec_idle_o_v6pcie7; 00540 pipe_rx1_polarity_o <= pipe_rx1_polarity_o_v6pcie9; 00541 pipe_tx1_compliance_o <= pipe_tx1_compliance_o_v6pcie54; 00542 pipe_tx1_char_is_k_o <= pipe_tx1_char_is_k_o_v6pcie53; 00543 pipe_tx1_data_o <= pipe_tx1_data_o_v6pcie55; 00544 pipe_tx1_elec_idle_o <= pipe_tx1_elec_idle_o_v6pcie56; 00545 pipe_tx1_powerdown_o <= pipe_tx1_powerdown_o_v6pcie57; 00546 pipe_rx2_valid_o <= pipe_rx2_valid_o_v6pcie17; 00547 pipe_rx2_chanisaligned_o <= pipe_rx2_chanisaligned_o_v6pcie12; 00548 pipe_rx2_status_o <= pipe_rx2_status_o_v6pcie16; 00549 pipe_rx2_phy_status_o <= pipe_rx2_phy_status_o_v6pcie14; 00550 pipe_rx2_elec_idle_o <= pipe_rx2_elec_idle_o_v6pcie13; 00551 pipe_rx2_polarity_o <= pipe_rx2_polarity_o_v6pcie15; 00552 pipe_tx2_compliance_o <= pipe_tx2_compliance_o_v6pcie59; 00553 pipe_tx2_char_is_k_o <= pipe_tx2_char_is_k_o_v6pcie58; 00554 pipe_tx2_data_o <= pipe_tx2_data_o_v6pcie60; 00555 pipe_tx2_elec_idle_o <= pipe_tx2_elec_idle_o_v6pcie61; 00556 pipe_tx2_powerdown_o <= pipe_tx2_powerdown_o_v6pcie62; 00557 pipe_rx3_valid_o <= pipe_rx3_valid_o_v6pcie23; 00558 pipe_rx3_chanisaligned_o <= pipe_rx3_chanisaligned_o_v6pcie18; 00559 pipe_rx3_status_o <= pipe_rx3_status_o_v6pcie22; 00560 pipe_rx3_phy_status_o <= pipe_rx3_phy_status_o_v6pcie20; 00561 pipe_rx3_elec_idle_o <= pipe_rx3_elec_idle_o_v6pcie19; 00562 pipe_rx3_polarity_o <= pipe_rx3_polarity_o_v6pcie21; 00563 pipe_tx3_compliance_o <= pipe_tx3_compliance_o_v6pcie64; 00564 pipe_tx3_char_is_k_o <= pipe_tx3_char_is_k_o_v6pcie63; 00565 pipe_tx3_data_o <= pipe_tx3_data_o_v6pcie65; 00566 pipe_tx3_elec_idle_o <= pipe_tx3_elec_idle_o_v6pcie66; 00567 pipe_tx3_powerdown_o <= pipe_tx3_powerdown_o_v6pcie67; 00568 pipe_rx4_valid_o <= pipe_rx4_valid_o_v6pcie29; 00569 pipe_rx4_chanisaligned_o <= pipe_rx4_chanisaligned_o_v6pcie24; 00570 pipe_rx4_status_o <= pipe_rx4_status_o_v6pcie28; 00571 pipe_rx4_phy_status_o <= pipe_rx4_phy_status_o_v6pcie26; 00572 pipe_rx4_elec_idle_o <= pipe_rx4_elec_idle_o_v6pcie25; 00573 pipe_rx4_polarity_o <= pipe_rx4_polarity_o_v6pcie27; 00574 pipe_tx4_compliance_o <= pipe_tx4_compliance_o_v6pcie69; 00575 pipe_tx4_char_is_k_o <= pipe_tx4_char_is_k_o_v6pcie68; 00576 pipe_tx4_data_o <= pipe_tx4_data_o_v6pcie70; 00577 pipe_tx4_elec_idle_o <= pipe_tx4_elec_idle_o_v6pcie71; 00578 pipe_tx4_powerdown_o <= pipe_tx4_powerdown_o_v6pcie72; 00579 pipe_rx5_valid_o <= pipe_rx5_valid_o_v6pcie35; 00580 pipe_rx5_chanisaligned_o <= pipe_rx5_chanisaligned_o_v6pcie30; 00581 pipe_rx5_status_o <= pipe_rx5_status_o_v6pcie34; 00582 pipe_rx5_phy_status_o <= pipe_rx5_phy_status_o_v6pcie32; 00583 pipe_rx5_elec_idle_o <= pipe_rx5_elec_idle_o_v6pcie31; 00584 pipe_rx5_polarity_o <= pipe_rx5_polarity_o_v6pcie33; 00585 pipe_tx5_compliance_o <= pipe_tx5_compliance_o_v6pcie74; 00586 pipe_tx5_char_is_k_o <= pipe_tx5_char_is_k_o_v6pcie73; 00587 pipe_tx5_data_o <= pipe_tx5_data_o_v6pcie75; 00588 pipe_tx5_elec_idle_o <= pipe_tx5_elec_idle_o_v6pcie76; 00589 pipe_tx5_powerdown_o <= pipe_tx5_powerdown_o_v6pcie77; 00590 pipe_rx6_valid_o <= pipe_rx6_valid_o_v6pcie41; 00591 pipe_rx6_chanisaligned_o <= pipe_rx6_chanisaligned_o_v6pcie36; 00592 pipe_rx6_status_o <= pipe_rx6_status_o_v6pcie40; 00593 pipe_rx6_phy_status_o <= pipe_rx6_phy_status_o_v6pcie38; 00594 pipe_rx6_elec_idle_o <= pipe_rx6_elec_idle_o_v6pcie37; 00595 pipe_rx6_polarity_o <= pipe_rx6_polarity_o_v6pcie39; 00596 pipe_tx6_compliance_o <= pipe_tx6_compliance_o_v6pcie79; 00597 pipe_tx6_char_is_k_o <= pipe_tx6_char_is_k_o_v6pcie78; 00598 pipe_tx6_data_o <= pipe_tx6_data_o_v6pcie80; 00599 pipe_tx6_elec_idle_o <= pipe_tx6_elec_idle_o_v6pcie81; 00600 pipe_tx6_powerdown_o <= pipe_tx6_powerdown_o_v6pcie82; 00601 pipe_rx7_valid_o <= pipe_rx7_valid_o_v6pcie47; 00602 pipe_rx7_chanisaligned_o <= pipe_rx7_chanisaligned_o_v6pcie42; 00603 pipe_rx7_status_o <= pipe_rx7_status_o_v6pcie46; 00604 pipe_rx7_phy_status_o <= pipe_rx7_phy_status_o_v6pcie44; 00605 pipe_rx7_elec_idle_o <= pipe_rx7_elec_idle_o_v6pcie43; 00606 pipe_rx7_polarity_o <= pipe_rx7_polarity_o_v6pcie45; 00607 pipe_tx7_compliance_o <= pipe_tx7_compliance_o_v6pcie84; 00608 pipe_tx7_char_is_k_o <= pipe_tx7_char_is_k_o_v6pcie83; 00609 pipe_tx7_data_o <= pipe_tx7_data_o_v6pcie85; 00610 pipe_tx7_elec_idle_o <= pipe_tx7_elec_idle_o_v6pcie86; 00611 pipe_tx7_powerdown_o <= pipe_tx7_powerdown_o_v6pcie87; 00612 00613 --synthesis translate_off 00614 -- initial begin 00615 -- $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES); 00616 -- end 00617 --synthesis translate_on 00618 00619 pipe_misc_i : pcie_pipe_misc_v6 00620 generic map ( 00621 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00622 ) 00623 port map ( 00624 00625 pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i, 00626 pipe_tx_reset_i => pipe_tx_reset_i, 00627 pipe_tx_rate_i => pipe_tx_rate_i, 00628 pipe_tx_deemph_i => pipe_tx_deemph_i, 00629 pipe_tx_margin_i => pipe_tx_margin_i, 00630 pipe_tx_swing_i => pipe_tx_swing_i, 00631 00632 pipe_tx_rcvr_det_o => pipe_tx_rcvr_det_o_v6pcie91, 00633 pipe_tx_reset_o => pipe_tx_reset_o_v6pcie92 , 00634 pipe_tx_rate_o => pipe_tx_rate_o_v6pcie90 , 00635 pipe_tx_deemph_o => pipe_tx_deemph_o_v6pcie88 , 00636 pipe_tx_margin_o => pipe_tx_margin_o_v6pcie89 , 00637 pipe_tx_swing_o => pipe_tx_swing_o_v6pcie93 , 00638 00639 pipe_clk => pipe_clk, 00640 rst_n => rst_n 00641 ); 00642 00643 pipe_lane_0_i : pcie_pipe_lane_v6 00644 generic map ( 00645 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00646 ) 00647 port map ( 00648 00649 pipe_rx_char_is_k_o => pipe_rx0_char_is_k_q, 00650 pipe_rx_data_o => pipe_rx0_data_q, 00651 pipe_rx_valid_o => pipe_rx0_valid_o_v6pcie5, 00652 pipe_rx_chanisaligned_o => pipe_rx0_chanisaligned_o_v6pcie0, 00653 pipe_rx_status_o => pipe_rx0_status_o_v6pcie4, 00654 pipe_rx_phy_status_o => pipe_rx0_phy_status_o_v6pcie2, 00655 pipe_rx_elec_idle_o => pipe_rx0_elec_idle_o_v6pcie1, 00656 pipe_rx_polarity_i => pipe_rx0_polarity_i, 00657 pipe_tx_compliance_i => pipe_tx0_compliance_i, 00658 pipe_tx_char_is_k_i => pipe_tx0_char_is_k_i, 00659 pipe_tx_data_i => pipe_tx0_data_i, 00660 pipe_tx_elec_idle_i => pipe_tx0_elec_idle_i, 00661 pipe_tx_powerdown_i => pipe_tx0_powerdown_i, 00662 00663 pipe_rx_char_is_k_i => pipe_rx0_char_is_k_i, 00664 pipe_rx_data_i => pipe_rx0_data_i, 00665 pipe_rx_valid_i => pipe_rx0_valid_i, 00666 pipe_rx_chanisaligned_i => pipe_rx0_chanisaligned_i, 00667 pipe_rx_status_i => pipe_rx0_status_i, 00668 pipe_rx_phy_status_i => pipe_rx0_phy_status_i, 00669 pipe_rx_elec_idle_i => pipe_rx0_elec_idle_i, 00670 pipe_rx_polarity_o => pipe_rx0_polarity_o_v6pcie3, 00671 pipe_tx_compliance_o => pipe_tx0_compliance_o_v6pcie49, 00672 pipe_tx_char_is_k_o => pipe_tx0_char_is_k_o_v6pcie48, 00673 pipe_tx_data_o => pipe_tx0_data_o_v6pcie50, 00674 pipe_tx_elec_idle_o => pipe_tx0_elec_idle_o_v6pcie51, 00675 pipe_tx_powerdown_o => pipe_tx0_powerdown_o_v6pcie52, 00676 00677 pipe_clk => pipe_clk, 00678 rst_n => rst_n 00679 ); 00680 00681 v6pcie94 : if (NO_OF_LANES >= 2) generate 00682 00683 pipe_lane_1_i : pcie_pipe_lane_v6 00684 generic map ( 00685 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00686 ) 00687 port map ( 00688 00689 pipe_rx_char_is_k_o => pipe_rx1_char_is_k_q, 00690 pipe_rx_data_o => pipe_rx1_data_q, 00691 pipe_rx_valid_o => pipe_rx1_valid_o_v6pcie11, 00692 pipe_rx_chanisaligned_o => pipe_rx1_chanisaligned_o_v6pcie6, 00693 pipe_rx_status_o => pipe_rx1_status_o_v6pcie10, 00694 pipe_rx_phy_status_o => pipe_rx1_phy_status_o_v6pcie8, 00695 pipe_rx_elec_idle_o => pipe_rx1_elec_idle_o_v6pcie7, 00696 pipe_rx_polarity_i => pipe_rx1_polarity_i, 00697 pipe_tx_compliance_i => pipe_tx1_compliance_i, 00698 pipe_tx_char_is_k_i => pipe_tx1_char_is_k_i, 00699 pipe_tx_data_i => pipe_tx1_data_i, 00700 pipe_tx_elec_idle_i => pipe_tx1_elec_idle_i, 00701 pipe_tx_powerdown_i => pipe_tx1_powerdown_i, 00702 00703 pipe_rx_char_is_k_i => pipe_rx1_char_is_k_i, 00704 pipe_rx_data_i => pipe_rx1_data_i, 00705 pipe_rx_valid_i => pipe_rx1_valid_i, 00706 pipe_rx_chanisaligned_i => pipe_rx1_chanisaligned_i, 00707 pipe_rx_status_i => pipe_rx1_status_i, 00708 pipe_rx_phy_status_i => pipe_rx1_phy_status_i, 00709 pipe_rx_elec_idle_i => pipe_rx1_elec_idle_i, 00710 pipe_rx_polarity_o => pipe_rx1_polarity_o_v6pcie9, 00711 pipe_tx_compliance_o => pipe_tx1_compliance_o_v6pcie54, 00712 pipe_tx_char_is_k_o => pipe_tx1_char_is_k_o_v6pcie53, 00713 pipe_tx_data_o => pipe_tx1_data_o_v6pcie55, 00714 pipe_tx_elec_idle_o => pipe_tx1_elec_idle_o_v6pcie56, 00715 pipe_tx_powerdown_o => pipe_tx1_powerdown_o_v6pcie57, 00716 00717 pipe_clk => pipe_clk, 00718 rst_n => rst_n 00719 ); 00720 00721 end generate; 00722 v6pcie95 : if (not(NO_OF_LANES >= 2)) generate 00723 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00724 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00725 pipe_rx1_char_is_k_q <= "00"; 00726 pipe_rx1_data_q <= "0000000000000000"; 00727 pipe_rx1_valid_o_v6pcie11 <= '0'; 00728 pipe_rx1_chanisaligned_o_v6pcie6 <= '0'; 00729 pipe_rx1_status_o_v6pcie10 <= "000"; 00730 pipe_rx1_phy_status_o_v6pcie8 <= '0'; 00731 pipe_rx1_elec_idle_o_v6pcie7 <= '1'; 00732 pipe_rx1_polarity_o_v6pcie9 <= '0'; 00733 pipe_tx1_compliance_o_v6pcie54 <= '0'; 00734 pipe_tx1_char_is_k_o_v6pcie53 <= "00"; 00735 pipe_tx1_data_o_v6pcie55 <= "0000000000000000"; 00736 pipe_tx1_elec_idle_o_v6pcie56 <= '1'; 00737 pipe_tx1_powerdown_o_v6pcie57 <= "00"; 00738 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00739 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00740 00741 end generate; 00742 v6pcie96 : if (NO_OF_LANES >= 4) generate 00743 pipe_lane_2_i : pcie_pipe_lane_v6 00744 generic map ( 00745 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00746 ) 00747 port map ( 00748 00749 pipe_rx_char_is_k_o => pipe_rx2_char_is_k_q, 00750 pipe_rx_data_o => pipe_rx2_data_q, 00751 pipe_rx_valid_o => pipe_rx2_valid_o_v6pcie17, 00752 pipe_rx_chanisaligned_o => pipe_rx2_chanisaligned_o_v6pcie12 , 00753 pipe_rx_status_o => pipe_rx2_status_o_v6pcie16, 00754 pipe_rx_phy_status_o => pipe_rx2_phy_status_o_v6pcie14, 00755 pipe_rx_elec_idle_o => pipe_rx2_elec_idle_o_v6pcie13, 00756 pipe_rx_polarity_i => pipe_rx2_polarity_i, 00757 pipe_tx_compliance_i => pipe_tx2_compliance_i, 00758 pipe_tx_char_is_k_i => pipe_tx2_char_is_k_i, 00759 pipe_tx_data_i => pipe_tx2_data_i, 00760 pipe_tx_elec_idle_i => pipe_tx2_elec_idle_i, 00761 pipe_tx_powerdown_i => pipe_tx2_powerdown_i, 00762 00763 pipe_rx_char_is_k_i => pipe_rx2_char_is_k_i, 00764 pipe_rx_data_i => pipe_rx2_data_i, 00765 pipe_rx_valid_i => pipe_rx2_valid_i, 00766 pipe_rx_chanisaligned_i => pipe_rx2_chanisaligned_i, 00767 pipe_rx_status_i => pipe_rx2_status_i, 00768 pipe_rx_phy_status_i => pipe_rx2_phy_status_i, 00769 pipe_rx_elec_idle_i => pipe_rx2_elec_idle_i, 00770 pipe_rx_polarity_o => pipe_rx2_polarity_o_v6pcie15, 00771 pipe_tx_compliance_o => pipe_tx2_compliance_o_v6pcie59, 00772 pipe_tx_char_is_k_o => pipe_tx2_char_is_k_o_v6pcie58, 00773 pipe_tx_data_o => pipe_tx2_data_o_v6pcie60, 00774 pipe_tx_elec_idle_o => pipe_tx2_elec_idle_o_v6pcie61, 00775 pipe_tx_powerdown_o => pipe_tx2_powerdown_o_v6pcie62, 00776 00777 pipe_clk => pipe_clk, 00778 rst_n => rst_n 00779 ); 00780 00781 pipe_lane_3_i : pcie_pipe_lane_v6 00782 generic map ( 00783 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00784 ) 00785 port map ( 00786 00787 pipe_rx_char_is_k_o => pipe_rx3_char_is_k_q, 00788 pipe_rx_data_o => pipe_rx3_data_q, 00789 pipe_rx_valid_o => pipe_rx3_valid_o_v6pcie23, 00790 pipe_rx_chanisaligned_o => pipe_rx3_chanisaligned_o_v6pcie18 , 00791 pipe_rx_status_o => pipe_rx3_status_o_v6pcie22, 00792 pipe_rx_phy_status_o => pipe_rx3_phy_status_o_v6pcie20, 00793 pipe_rx_elec_idle_o => pipe_rx3_elec_idle_o_v6pcie19, 00794 pipe_rx_polarity_i => pipe_rx3_polarity_i, 00795 pipe_tx_compliance_i => pipe_tx3_compliance_i, 00796 pipe_tx_char_is_k_i => pipe_tx3_char_is_k_i, 00797 pipe_tx_data_i => pipe_tx3_data_i, 00798 pipe_tx_elec_idle_i => pipe_tx3_elec_idle_i, 00799 pipe_tx_powerdown_i => pipe_tx3_powerdown_i, 00800 00801 pipe_rx_char_is_k_i => pipe_rx3_char_is_k_i, 00802 pipe_rx_data_i => pipe_rx3_data_i, 00803 pipe_rx_valid_i => pipe_rx3_valid_i, 00804 pipe_rx_chanisaligned_i => pipe_rx3_chanisaligned_i, 00805 pipe_rx_status_i => pipe_rx3_status_i, 00806 pipe_rx_phy_status_i => pipe_rx3_phy_status_i, 00807 pipe_rx_elec_idle_i => pipe_rx3_elec_idle_i, 00808 pipe_rx_polarity_o => pipe_rx3_polarity_o_v6pcie21, 00809 pipe_tx_compliance_o => pipe_tx3_compliance_o_v6pcie64, 00810 pipe_tx_char_is_k_o => pipe_tx3_char_is_k_o_v6pcie63, 00811 pipe_tx_data_o => pipe_tx3_data_o_v6pcie65, 00812 pipe_tx_elec_idle_o => pipe_tx3_elec_idle_o_v6pcie66, 00813 pipe_tx_powerdown_o => pipe_tx3_powerdown_o_v6pcie67, 00814 00815 pipe_clk => pipe_clk, 00816 rst_n => rst_n 00817 ); 00818 00819 end generate; 00820 v6pcie97 : if (not(NO_OF_LANES >= 4)) generate 00821 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00822 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00823 pipe_rx2_char_is_k_q <= "00"; 00824 pipe_rx2_data_q <= "0000000000000000"; 00825 pipe_rx2_valid_o_v6pcie17 <= '0'; 00826 pipe_rx2_chanisaligned_o_v6pcie12 <= '0'; 00827 pipe_rx2_status_o_v6pcie16 <= "000"; 00828 pipe_rx2_phy_status_o_v6pcie14 <= '0'; 00829 pipe_rx2_elec_idle_o_v6pcie13 <= '1'; 00830 pipe_rx2_polarity_o_v6pcie15 <= '0'; 00831 pipe_tx2_compliance_o_v6pcie59 <= '0'; 00832 pipe_tx2_char_is_k_o_v6pcie58 <= "00"; 00833 pipe_tx2_data_o_v6pcie60 <= "0000000000000000"; 00834 pipe_tx2_elec_idle_o_v6pcie61 <= '1'; 00835 pipe_tx2_powerdown_o_v6pcie62 <= "00"; 00836 00837 pipe_rx3_char_is_k_q <= "00"; 00838 pipe_rx3_data_q <= "0000000000000000"; 00839 pipe_rx3_valid_o_v6pcie23 <= '0'; 00840 pipe_rx3_chanisaligned_o_v6pcie18 <= '0'; 00841 pipe_rx3_status_o_v6pcie22 <= "000"; 00842 pipe_rx3_phy_status_o_v6pcie20 <= '0'; 00843 pipe_rx3_elec_idle_o_v6pcie19 <= '1'; 00844 pipe_rx3_polarity_o_v6pcie21 <= '0'; 00845 pipe_tx3_compliance_o_v6pcie64 <= '0'; 00846 pipe_tx3_char_is_k_o_v6pcie63 <= "00"; 00847 pipe_tx3_data_o_v6pcie65 <= "0000000000000000"; 00848 pipe_tx3_elec_idle_o_v6pcie66 <= '1'; 00849 pipe_tx3_powerdown_o_v6pcie67 <= "00"; 00850 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00851 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 00852 00853 end generate; 00854 v6pcie98 : if (NO_OF_LANES >= 8) generate 00855 00856 pipe_lane_4_i : pcie_pipe_lane_v6 00857 generic map ( 00858 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00859 ) 00860 port map ( 00861 00862 pipe_rx_char_is_k_o => pipe_rx4_char_is_k_q, 00863 pipe_rx_data_o => pipe_rx4_data_q, 00864 pipe_rx_valid_o => pipe_rx4_valid_o_v6pcie29, 00865 pipe_rx_chanisaligned_o => pipe_rx4_chanisaligned_o_v6pcie24 , 00866 pipe_rx_status_o => pipe_rx4_status_o_v6pcie28, 00867 pipe_rx_phy_status_o => pipe_rx4_phy_status_o_v6pcie26, 00868 pipe_rx_elec_idle_o => pipe_rx4_elec_idle_o_v6pcie25, 00869 pipe_rx_polarity_i => pipe_rx4_polarity_i, 00870 pipe_tx_compliance_i => pipe_tx4_compliance_i, 00871 pipe_tx_char_is_k_i => pipe_tx4_char_is_k_i, 00872 pipe_tx_data_i => pipe_tx4_data_i, 00873 pipe_tx_elec_idle_i => pipe_tx4_elec_idle_i, 00874 pipe_tx_powerdown_i => pipe_tx4_powerdown_i, 00875 00876 pipe_rx_char_is_k_i => pipe_rx4_char_is_k_i, 00877 pipe_rx_data_i => pipe_rx4_data_i, 00878 pipe_rx_valid_i => pipe_rx4_valid_i, 00879 pipe_rx_chanisaligned_i => pipe_rx4_chanisaligned_i, 00880 pipe_rx_status_i => pipe_rx4_status_i, 00881 pipe_rx_phy_status_i => pipe_rx4_phy_status_i, 00882 pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i, 00883 pipe_rx_polarity_o => pipe_rx4_polarity_o_v6pcie27, 00884 pipe_tx_compliance_o => pipe_tx4_compliance_o_v6pcie69, 00885 pipe_tx_char_is_k_o => pipe_tx4_char_is_k_o_v6pcie68, 00886 pipe_tx_data_o => pipe_tx4_data_o_v6pcie70, 00887 pipe_tx_elec_idle_o => pipe_tx4_elec_idle_o_v6pcie71, 00888 pipe_tx_powerdown_o => pipe_tx4_powerdown_o_v6pcie72, 00889 00890 pipe_clk => pipe_clk, 00891 rst_n => rst_n 00892 ); 00893 00894 pipe_lane_5_i : pcie_pipe_lane_v6 00895 generic map ( 00896 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00897 ) 00898 port map ( 00899 00900 pipe_rx_char_is_k_o => pipe_rx5_char_is_k_q, 00901 pipe_rx_data_o => pipe_rx5_data_q, 00902 pipe_rx_valid_o => pipe_rx5_valid_o_v6pcie35, 00903 pipe_rx_chanisaligned_o => pipe_rx5_chanisaligned_o_v6pcie30 , 00904 pipe_rx_status_o => pipe_rx5_status_o_v6pcie34, 00905 pipe_rx_phy_status_o => pipe_rx5_phy_status_o_v6pcie32, 00906 pipe_rx_elec_idle_o => pipe_rx5_elec_idle_o_v6pcie31, 00907 pipe_rx_polarity_i => pipe_rx5_polarity_i, 00908 pipe_tx_compliance_i => pipe_tx5_compliance_i, 00909 pipe_tx_char_is_k_i => pipe_tx5_char_is_k_i, 00910 pipe_tx_data_i => pipe_tx5_data_i, 00911 pipe_tx_elec_idle_i => pipe_tx5_elec_idle_i, 00912 pipe_tx_powerdown_i => pipe_tx5_powerdown_i, 00913 00914 pipe_rx_char_is_k_i => pipe_rx5_char_is_k_i, 00915 pipe_rx_data_i => pipe_rx5_data_i, 00916 pipe_rx_valid_i => pipe_rx5_valid_i, 00917 pipe_rx_chanisaligned_i => pipe_rx5_chanisaligned_i, 00918 pipe_rx_status_i => pipe_rx5_status_i, 00919 pipe_rx_phy_status_i => pipe_rx4_phy_status_i, 00920 pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i, 00921 pipe_rx_polarity_o => pipe_rx5_polarity_o_v6pcie33, 00922 pipe_tx_compliance_o => pipe_tx5_compliance_o_v6pcie74, 00923 pipe_tx_char_is_k_o => pipe_tx5_char_is_k_o_v6pcie73, 00924 pipe_tx_data_o => pipe_tx5_data_o_v6pcie75, 00925 pipe_tx_elec_idle_o => pipe_tx5_elec_idle_o_v6pcie76, 00926 pipe_tx_powerdown_o => pipe_tx5_powerdown_o_v6pcie77, 00927 00928 pipe_clk => pipe_clk, 00929 rst_n => rst_n 00930 ); 00931 00932 pipe_lane_6_i : pcie_pipe_lane_v6 00933 generic map ( 00934 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00935 ) 00936 port map ( 00937 00938 pipe_rx_char_is_k_o => pipe_rx6_char_is_k_q, 00939 pipe_rx_data_o => pipe_rx6_data_q, 00940 pipe_rx_valid_o => pipe_rx6_valid_o_v6pcie41, 00941 pipe_rx_chanisaligned_o => pipe_rx6_chanisaligned_o_v6pcie36 , 00942 pipe_rx_status_o => pipe_rx6_status_o_v6pcie40, 00943 pipe_rx_phy_status_o => pipe_rx6_phy_status_o_v6pcie38, 00944 pipe_rx_elec_idle_o => pipe_rx6_elec_idle_o_v6pcie37, 00945 pipe_rx_polarity_i => pipe_rx6_polarity_i, 00946 pipe_tx_compliance_i => pipe_tx6_compliance_i, 00947 pipe_tx_char_is_k_i => pipe_tx6_char_is_k_i, 00948 pipe_tx_data_i => pipe_tx6_data_i, 00949 pipe_tx_elec_idle_i => pipe_tx6_elec_idle_i, 00950 pipe_tx_powerdown_i => pipe_tx6_powerdown_i, 00951 00952 pipe_rx_char_is_k_i => pipe_rx6_char_is_k_i, 00953 pipe_rx_data_i => pipe_rx6_data_i, 00954 pipe_rx_valid_i => pipe_rx6_valid_i, 00955 pipe_rx_chanisaligned_i => pipe_rx6_chanisaligned_i, 00956 pipe_rx_status_i => pipe_rx6_status_i, 00957 pipe_rx_phy_status_i => pipe_rx4_phy_status_i, 00958 pipe_rx_elec_idle_i => pipe_rx6_elec_idle_i, 00959 pipe_rx_polarity_o => pipe_rx6_polarity_o_v6pcie39, 00960 pipe_tx_compliance_o => pipe_tx6_compliance_o_v6pcie79, 00961 pipe_tx_char_is_k_o => pipe_tx6_char_is_k_o_v6pcie78, 00962 pipe_tx_data_o => pipe_tx6_data_o_v6pcie80, 00963 pipe_tx_elec_idle_o => pipe_tx6_elec_idle_o_v6pcie81, 00964 pipe_tx_powerdown_o => pipe_tx6_powerdown_o_v6pcie82, 00965 00966 pipe_clk => pipe_clk, 00967 rst_n => rst_n 00968 ); 00969 00970 pipe_lane_7_i : pcie_pipe_lane_v6 00971 generic map ( 00972 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES 00973 ) 00974 port map ( 00975 00976 pipe_rx_char_is_k_o => pipe_rx7_char_is_k_q, 00977 pipe_rx_data_o => pipe_rx7_data_q, 00978 pipe_rx_valid_o => pipe_rx7_valid_o_v6pcie47, 00979 pipe_rx_chanisaligned_o => pipe_rx7_chanisaligned_o_v6pcie42 , 00980 pipe_rx_status_o => pipe_rx7_status_o_v6pcie46, 00981 pipe_rx_phy_status_o => pipe_rx7_phy_status_o_v6pcie44, 00982 pipe_rx_elec_idle_o => pipe_rx7_elec_idle_o_v6pcie43, 00983 pipe_rx_polarity_i => pipe_rx7_polarity_i, 00984 pipe_tx_compliance_i => pipe_tx7_compliance_i, 00985 pipe_tx_char_is_k_i => pipe_tx7_char_is_k_i, 00986 pipe_tx_data_i => pipe_tx7_data_i, 00987 pipe_tx_elec_idle_i => pipe_tx7_elec_idle_i, 00988 pipe_tx_powerdown_i => pipe_tx7_powerdown_i, 00989 00990 pipe_rx_char_is_k_i => pipe_rx7_char_is_k_i, 00991 pipe_rx_data_i => pipe_rx7_data_i, 00992 pipe_rx_valid_i => pipe_rx7_valid_i, 00993 pipe_rx_chanisaligned_i => pipe_rx7_chanisaligned_i, 00994 pipe_rx_status_i => pipe_rx7_status_i, 00995 pipe_rx_phy_status_i => pipe_rx4_phy_status_i, 00996 pipe_rx_elec_idle_i => pipe_rx7_elec_idle_i, 00997 pipe_rx_polarity_o => pipe_rx7_polarity_o_v6pcie45, 00998 pipe_tx_compliance_o => pipe_tx7_compliance_o_v6pcie84, 00999 pipe_tx_char_is_k_o => pipe_tx7_char_is_k_o_v6pcie83, 01000 pipe_tx_data_o => pipe_tx7_data_o_v6pcie85, 01001 pipe_tx_elec_idle_o => pipe_tx7_elec_idle_o_v6pcie86, 01002 pipe_tx_powerdown_o => pipe_tx7_powerdown_o_v6pcie87, 01003 01004 pipe_clk => pipe_clk, 01005 rst_n => rst_n 01006 ); 01007 01008 end generate; 01009 v6pcie99 : if (not(NO_OF_LANES >= 8)) generate 01010 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01011 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01012 pipe_rx4_char_is_k_q <= "00"; 01013 pipe_rx4_data_q <= "0000000000000000"; 01014 pipe_rx4_valid_o_v6pcie29 <= '0'; 01015 pipe_rx4_chanisaligned_o_v6pcie24 <= '0'; 01016 pipe_rx4_status_o_v6pcie28 <= "000"; 01017 pipe_rx4_phy_status_o_v6pcie26 <= '0'; 01018 pipe_rx4_elec_idle_o_v6pcie25 <= '1'; 01019 pipe_rx4_polarity_o_v6pcie27 <= '0'; 01020 pipe_tx4_compliance_o_v6pcie69 <= '0'; 01021 pipe_tx4_char_is_k_o_v6pcie68 <= "00"; 01022 pipe_tx4_data_o_v6pcie70 <= "0000000000000000"; 01023 pipe_tx4_elec_idle_o_v6pcie71 <= '1'; 01024 pipe_tx4_powerdown_o_v6pcie72 <= "00"; 01025 01026 pipe_rx5_char_is_k_q <= "00"; 01027 pipe_rx5_data_q <= "0000000000000000"; 01028 pipe_rx5_valid_o_v6pcie35 <= '0'; 01029 pipe_rx5_chanisaligned_o_v6pcie30 <= '0'; 01030 pipe_rx5_status_o_v6pcie34 <= "000"; 01031 pipe_rx5_phy_status_o_v6pcie32 <= '0'; 01032 pipe_rx5_elec_idle_o_v6pcie31 <= '1'; 01033 pipe_rx5_polarity_o_v6pcie33 <= '0'; 01034 pipe_tx5_compliance_o_v6pcie74 <= '0'; 01035 pipe_tx5_char_is_k_o_v6pcie73 <= "00"; 01036 pipe_tx5_data_o_v6pcie75 <= "0000000000000000"; 01037 pipe_tx5_elec_idle_o_v6pcie76 <= '1'; 01038 pipe_tx5_powerdown_o_v6pcie77 <= "00"; 01039 01040 pipe_rx6_char_is_k_q <= "00"; 01041 pipe_rx6_data_q <= "0000000000000000"; 01042 pipe_rx6_valid_o_v6pcie41 <= '0'; 01043 pipe_rx6_chanisaligned_o_v6pcie36 <= '0'; 01044 pipe_rx6_status_o_v6pcie40 <= "000"; 01045 pipe_rx6_phy_status_o_v6pcie38 <= '0'; 01046 pipe_rx6_elec_idle_o_v6pcie37 <= '1'; 01047 pipe_rx6_polarity_o_v6pcie39 <= '0'; 01048 pipe_tx6_compliance_o_v6pcie79 <= '0'; 01049 pipe_tx6_char_is_k_o_v6pcie78 <= "00"; 01050 pipe_tx6_data_o_v6pcie80 <= "0000000000000000"; 01051 pipe_tx6_elec_idle_o_v6pcie81 <= '1'; 01052 pipe_tx6_powerdown_o_v6pcie82 <= "00"; 01053 01054 pipe_rx7_char_is_k_q <= "00"; 01055 pipe_rx7_data_q <= "0000000000000000"; 01056 pipe_rx7_valid_o_v6pcie47 <= '0'; 01057 pipe_rx7_chanisaligned_o_v6pcie42 <= '0'; 01058 pipe_rx7_status_o_v6pcie46 <= "000"; 01059 pipe_rx7_phy_status_o_v6pcie44 <= '0'; 01060 pipe_rx7_elec_idle_o_v6pcie43 <= '1'; 01061 pipe_rx7_polarity_o_v6pcie45 <= '0'; 01062 pipe_tx7_compliance_o_v6pcie84 <= '0'; 01063 pipe_tx7_char_is_k_o_v6pcie83 <= "00"; 01064 pipe_tx7_data_o_v6pcie85 <= "0000000000000000"; 01065 pipe_tx7_elec_idle_o_v6pcie86 <= '1'; 01066 pipe_tx7_powerdown_o_v6pcie87 <= "00"; 01067 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01068 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01069 01070 end generate; 01071 01072 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01073 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01074 01075 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01076 --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 01077 01078 pipe_rx0_char_is_k_o <= pipe_rx0_char_is_k_q; 01079 pipe_rx0_data_o <= pipe_rx0_data_q; 01080 pipe_rx1_char_is_k_o <= pipe_rx1_char_is_k_q; 01081 pipe_rx1_data_o <= pipe_rx1_data_q; 01082 pipe_rx2_char_is_k_o <= pipe_rx2_char_is_k_q; 01083 pipe_rx2_data_o <= pipe_rx2_data_q; 01084 pipe_rx3_char_is_k_o <= pipe_rx3_char_is_k_q; 01085 pipe_rx3_data_o <= pipe_rx3_data_q; 01086 pipe_rx4_char_is_k_o <= pipe_rx4_char_is_k_q; 01087 pipe_rx4_data_o <= pipe_rx4_data_q; 01088 pipe_rx5_char_is_k_o <= pipe_rx5_char_is_k_q; 01089 pipe_rx5_data_o <= pipe_rx5_data_q; 01090 pipe_rx6_char_is_k_o <= pipe_rx6_char_is_k_q; 01091 pipe_rx6_data_o <= pipe_rx6_data_q; 01092 pipe_rx7_char_is_k_o <= pipe_rx7_char_is_k_q; 01093 pipe_rx7_data_o <= pipe_rx7_data_q; 01094 01095 end v6_pcie;
1.7.4