DS_DMA
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Design Unit List
Файлы
Классы
Design Units
Design Unit Hierarchy
Design Unit Members
pcie_pipe_v6
v6_pcie
Components
|
Constants
|
Signals
|
Component Instantiations
v6_pcie Architecture Reference
Граф наследования:v6_pcie:
Полный список членов класса
Components
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pcie_pipe_misc_v6
<Entity pcie_pipe_misc_v6>
Constants
Tc2o
integer
:
=
1
Signals
pipe_rx0_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx0_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx1_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx1_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx2_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx2_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx3_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx3_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx4_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx4_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx5_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx5_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx6_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx6_data_q
std_logic_vector
(
15
downto
0
)
pipe_rx7_char_is_k_q
std_logic_vector
(
1
downto
0
)
pipe_rx7_data_q
std_logic_vector
(
15
downto
0
)
pipe_tx_rcvr_det_o_v6pcie91
std_logic
pipe_tx_reset_o_v6pcie92
std_logic
pipe_tx_rate_o_v6pcie90
std_logic
pipe_tx_deemph_o_v6pcie88
std_logic
pipe_tx_margin_o_v6pcie89
std_logic_vector
(
2
downto
0
)
pipe_tx_swing_o_v6pcie93
std_logic
pipe_rx0_valid_o_v6pcie5
std_logic
pipe_rx0_chanisaligned_o_v6pcie0
std_logic
pipe_rx0_status_o_v6pcie4
std_logic_vector
(
2
downto
0
)
pipe_rx0_phy_status_o_v6pcie2
std_logic
pipe_rx0_elec_idle_o_v6pcie1
std_logic
pipe_rx0_polarity_o_v6pcie3
std_logic
pipe_tx0_compliance_o_v6pcie49
std_logic
pipe_tx0_char_is_k_o_v6pcie48
std_logic_vector
(
1
downto
0
)
pipe_tx0_data_o_v6pcie50
std_logic_vector
(
15
downto
0
)
pipe_tx0_elec_idle_o_v6pcie51
std_logic
pipe_tx0_powerdown_o_v6pcie52
std_logic_vector
(
1
downto
0
)
pipe_rx1_valid_o_v6pcie11
std_logic
pipe_rx1_chanisaligned_o_v6pcie6
std_logic
pipe_rx1_status_o_v6pcie10
std_logic_vector
(
2
downto
0
)
pipe_rx1_phy_status_o_v6pcie8
std_logic
pipe_rx1_elec_idle_o_v6pcie7
std_logic
pipe_rx1_polarity_o_v6pcie9
std_logic
pipe_tx1_compliance_o_v6pcie54
std_logic
pipe_tx1_char_is_k_o_v6pcie53
std_logic_vector
(
1
downto
0
)
pipe_tx1_data_o_v6pcie55
std_logic_vector
(
15
downto
0
)
pipe_tx1_elec_idle_o_v6pcie56
std_logic
pipe_tx1_powerdown_o_v6pcie57
std_logic_vector
(
1
downto
0
)
pipe_rx2_valid_o_v6pcie17
std_logic
pipe_rx2_chanisaligned_o_v6pcie12
std_logic
pipe_rx2_status_o_v6pcie16
std_logic_vector
(
2
downto
0
)
pipe_rx2_phy_status_o_v6pcie14
std_logic
pipe_rx2_elec_idle_o_v6pcie13
std_logic
pipe_rx2_polarity_o_v6pcie15
std_logic
pipe_tx2_compliance_o_v6pcie59
std_logic
pipe_tx2_char_is_k_o_v6pcie58
std_logic_vector
(
1
downto
0
)
pipe_tx2_data_o_v6pcie60
std_logic_vector
(
15
downto
0
)
pipe_tx2_elec_idle_o_v6pcie61
std_logic
pipe_tx2_powerdown_o_v6pcie62
std_logic_vector
(
1
downto
0
)
pipe_rx3_valid_o_v6pcie23
std_logic
pipe_rx3_chanisaligned_o_v6pcie18
std_logic
pipe_rx3_status_o_v6pcie22
std_logic_vector
(
2
downto
0
)
pipe_rx3_phy_status_o_v6pcie20
std_logic
pipe_rx3_elec_idle_o_v6pcie19
std_logic
pipe_rx3_polarity_o_v6pcie21
std_logic
pipe_tx3_compliance_o_v6pcie64
std_logic
pipe_tx3_char_is_k_o_v6pcie63
std_logic_vector
(
1
downto
0
)
pipe_tx3_data_o_v6pcie65
std_logic_vector
(
15
downto
0
)
pipe_tx3_elec_idle_o_v6pcie66
std_logic
pipe_tx3_powerdown_o_v6pcie67
std_logic_vector
(
1
downto
0
)
pipe_rx4_valid_o_v6pcie29
std_logic
pipe_rx4_chanisaligned_o_v6pcie24
std_logic
pipe_rx4_status_o_v6pcie28
std_logic_vector
(
2
downto
0
)
pipe_rx4_phy_status_o_v6pcie26
std_logic
pipe_rx4_elec_idle_o_v6pcie25
std_logic
pipe_rx4_polarity_o_v6pcie27
std_logic
pipe_tx4_compliance_o_v6pcie69
std_logic
pipe_tx4_char_is_k_o_v6pcie68
std_logic_vector
(
1
downto
0
)
pipe_tx4_data_o_v6pcie70
std_logic_vector
(
15
downto
0
)
pipe_tx4_elec_idle_o_v6pcie71
std_logic
pipe_tx4_powerdown_o_v6pcie72
std_logic_vector
(
1
downto
0
)
pipe_rx5_valid_o_v6pcie35
std_logic
pipe_rx5_chanisaligned_o_v6pcie30
std_logic
pipe_rx5_status_o_v6pcie34
std_logic_vector
(
2
downto
0
)
pipe_rx5_phy_status_o_v6pcie32
std_logic
pipe_rx5_elec_idle_o_v6pcie31
std_logic
pipe_rx5_polarity_o_v6pcie33
std_logic
pipe_tx5_compliance_o_v6pcie74
std_logic
pipe_tx5_char_is_k_o_v6pcie73
std_logic_vector
(
1
downto
0
)
pipe_tx5_data_o_v6pcie75
std_logic_vector
(
15
downto
0
)
pipe_tx5_elec_idle_o_v6pcie76
std_logic
pipe_tx5_powerdown_o_v6pcie77
std_logic_vector
(
1
downto
0
)
pipe_rx6_valid_o_v6pcie41
std_logic
pipe_rx6_chanisaligned_o_v6pcie36
std_logic
pipe_rx6_status_o_v6pcie40
std_logic_vector
(
2
downto
0
)
pipe_rx6_phy_status_o_v6pcie38
std_logic
pipe_rx6_elec_idle_o_v6pcie37
std_logic
pipe_rx6_polarity_o_v6pcie39
std_logic
pipe_tx6_compliance_o_v6pcie79
std_logic
pipe_tx6_char_is_k_o_v6pcie78
std_logic_vector
(
1
downto
0
)
pipe_tx6_data_o_v6pcie80
std_logic_vector
(
15
downto
0
)
pipe_tx6_elec_idle_o_v6pcie81
std_logic
pipe_tx6_powerdown_o_v6pcie82
std_logic_vector
(
1
downto
0
)
pipe_rx7_valid_o_v6pcie47
std_logic
pipe_rx7_chanisaligned_o_v6pcie42
std_logic
pipe_rx7_status_o_v6pcie46
std_logic_vector
(
2
downto
0
)
pipe_rx7_phy_status_o_v6pcie44
std_logic
pipe_rx7_elec_idle_o_v6pcie43
std_logic
pipe_rx7_polarity_o_v6pcie45
std_logic
pipe_tx7_compliance_o_v6pcie84
std_logic
pipe_tx7_char_is_k_o_v6pcie83
std_logic_vector
(
1
downto
0
)
pipe_tx7_data_o_v6pcie85
std_logic_vector
(
15
downto
0
)
pipe_tx7_elec_idle_o_v6pcie86
std_logic
pipe_tx7_powerdown_o_v6pcie87
std_logic_vector
(
1
downto
0
)
Component Instantiations
pipe_misc_i
pcie_pipe_misc_v6
<Entity pcie_pipe_misc_v6>
pipe_lane_0_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_1_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_2_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_3_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_4_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_5_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_6_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
pipe_lane_7_i
pcie_pipe_lane_v6
<Entity pcie_pipe_lane_v6>
Подробное описание
См. определение в файле
pcie_pipe_v6.vhd
строка
339
Объявления и описания членов класса находятся в файле:
pcie_src/pcie_core64_m1/source_virtex6/
pcie_pipe_v6.vhd
Документация по DS_DMA. Последние изменения: Чт 22 Сен 2011 11:51:38. Создано системой
1.7.4