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DS_DMA
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00001 ------------------------------------------------------------------------------- 00002 -- 00003 -- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 -- 00049 ------------------------------------------------------------------------------- 00050 -- Project : Virtex-6 Integrated Block for PCI Express 00051 -- File : cl_v6pcie_m1.vhd 00052 -- Version : 2.3 00053 -- Description: Virtex6 solution wrapper : Endpoint for PCI Express 00054 -- 00055 -- 00056 -- 00057 -------------------------------------------------------------------------------- 00058 00059 library ieee; 00060 use ieee.std_logic_1164.all; 00061 use ieee.std_logic_unsigned.all; 00062 00063 library unisim; 00064 use unisim.vcomponents.all; 00065 00066 entity cl_v6pcie_m1 is 00067 generic ( 00068 PCIE_DRP_ENABLE : boolean := FALSE; 00069 ALLOW_X8_GEN2 : boolean := FALSE; 00070 BAR0 : bit_vector := X"FFE00000"; 00071 BAR1 : bit_vector := X"FFE00000"; 00072 BAR2 : bit_vector := X"00000000"; 00073 BAR3 : bit_vector := X"00000000"; 00074 BAR4 : bit_vector := X"00000000"; 00075 BAR5 : bit_vector := X"00000000"; 00076 00077 CARDBUS_CIS_POINTER : bit_vector := X"00000000"; 00078 CLASS_CODE : bit_vector := X"FFFFFF"; 00079 CMD_INTX_IMPLEMENTED : boolean := TRUE; 00080 CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE; 00081 CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"2"; 00082 00083 DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0; 00084 DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7; 00085 DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE; 00086 DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 1; 00087 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0; 00088 DEVICE_ID : bit_vector := X"5507"; 00089 00090 DISABLE_LANE_REVERSAL : boolean := TRUE; 00091 DISABLE_SCRAMBLING : boolean := FALSE; 00092 DSN_BASE_PTR : bit_vector := X"0"; 00093 DSN_CAP_NEXTPTR : bit_vector := X"000"; 00094 DSN_CAP_ON : boolean := FALSE; 00095 00096 ENABLE_MSG_ROUTE : bit_vector := "00000000000"; 00097 ENABLE_RX_TD_ECRC_TRIM : boolean := TRUE; 00098 EXPANSION_ROM : bit_vector := X"00000000"; 00099 EXT_CFG_CAP_PTR : bit_vector := X"3F"; 00100 EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF"; 00101 HEADER_TYPE : bit_vector := X"00"; 00102 INTERRUPT_PIN : bit_vector := X"1"; 00103 00104 LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE; 00105 LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE; 00106 LINK_CAP_MAX_LINK_SPEED : bit_vector := X"2"; 00107 LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"04"; 00108 LINK_CAP_MAX_LINK_WIDTH_int : integer := 4; 00109 LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE; 00110 00111 LINK_CTRL2_DEEMPHASIS : boolean := FALSE; 00112 LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE; 00113 LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2"; 00114 LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE; 00115 00116 LL_ACK_TIMEOUT : bit_vector := X"0000"; 00117 LL_ACK_TIMEOUT_EN : boolean := FALSE; 00118 LL_ACK_TIMEOUT_FUNC : integer := 0; 00119 LL_REPLAY_TIMEOUT : bit_vector := X"0026"; 00120 LL_REPLAY_TIMEOUT_EN : boolean := TRUE; 00121 LL_REPLAY_TIMEOUT_FUNC : integer := 1; 00122 00123 LTSSM_MAX_LINK_WIDTH : bit_vector := X"04"; 00124 MSI_CAP_MULTIMSGCAP : integer := 0; 00125 MSI_CAP_MULTIMSG_EXTENSION : integer := 0; 00126 MSI_CAP_ON : boolean := FALSE; 00127 MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := FALSE; 00128 MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE; 00129 00130 MSIX_CAP_ON : boolean := FALSE; 00131 MSIX_CAP_PBA_BIR : integer := 0; 00132 MSIX_CAP_PBA_OFFSET : bit_vector := X"0"; 00133 MSIX_CAP_TABLE_BIR : integer := 0; 00134 MSIX_CAP_TABLE_OFFSET : bit_vector := X"0"; 00135 MSIX_CAP_TABLE_SIZE : bit_vector := X"000"; 00136 00137 PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0"; 00138 PCIE_CAP_INT_MSG_NUM : bit_vector := X"1"; 00139 PCIE_CAP_NEXTPTR : bit_vector := X"00"; 00140 PIPE_PIPELINE_STAGES : integer := 0; -- 0 - 0 stages; 1 - 1 stage; 2 - 2 stages 00141 00142 PM_CAP_DSI : boolean := FALSE; 00143 PM_CAP_D1SUPPORT : boolean := FALSE; 00144 PM_CAP_D2SUPPORT : boolean := FALSE; 00145 PM_CAP_NEXTPTR : bit_vector := X"60"; 00146 PM_CAP_PMESUPPORT : bit_vector := X"0F"; 00147 PM_CSR_NOSOFTRST : boolean := TRUE; 00148 00149 PM_DATA_SCALE0 : bit_vector := X"0"; 00150 PM_DATA_SCALE1 : bit_vector := X"0"; 00151 PM_DATA_SCALE2 : bit_vector := X"0"; 00152 PM_DATA_SCALE3 : bit_vector := X"0"; 00153 PM_DATA_SCALE4 : bit_vector := X"0"; 00154 PM_DATA_SCALE5 : bit_vector := X"0"; 00155 PM_DATA_SCALE6 : bit_vector := X"0"; 00156 PM_DATA_SCALE7 : bit_vector := X"0"; 00157 00158 PM_DATA0 : bit_vector := X"00"; 00159 PM_DATA1 : bit_vector := X"00"; 00160 PM_DATA2 : bit_vector := X"00"; 00161 PM_DATA3 : bit_vector := X"00"; 00162 PM_DATA4 : bit_vector := X"00"; 00163 PM_DATA5 : bit_vector := X"00"; 00164 PM_DATA6 : bit_vector := X"00"; 00165 PM_DATA7 : bit_vector := X"00"; 00166 00167 REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz; 1 - 125 MHz; 2 - 250 MHz 00168 REVISION_ID : bit_vector := X"20"; 00169 SPARE_BIT0 : integer := 0; 00170 SUBSYSTEM_ID : bit_vector := X"0002"; 00171 SUBSYSTEM_VENDOR_ID : bit_vector := X"4953"; 00172 00173 TL_RX_RAM_RADDR_LATENCY : integer := 0; 00174 TL_RX_RAM_RDATA_LATENCY : integer := 2; 00175 TL_RX_RAM_WRITE_LATENCY : integer := 0; 00176 TL_TX_RAM_RADDR_LATENCY : integer := 0; 00177 TL_TX_RAM_RDATA_LATENCY : integer := 2; 00178 TL_TX_RAM_WRITE_LATENCY : integer := 0; 00179 00180 UPCONFIG_CAPABLE : boolean := TRUE; 00181 USER_CLK_FREQ : integer := 3; 00182 VC_BASE_PTR : bit_vector := X"0"; 00183 VC_CAP_NEXTPTR : bit_vector := X"000"; 00184 VC_CAP_ON : boolean := FALSE; 00185 VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE; 00186 00187 VC0_CPL_INFINITE : boolean := TRUE; 00188 VC0_RX_RAM_LIMIT : bit_vector := X"3FF"; 00189 VC0_TOTAL_CREDITS_CD : integer := 378; 00190 VC0_TOTAL_CREDITS_CH : integer := 36; 00191 VC0_TOTAL_CREDITS_NPH : integer := 12; 00192 VC0_TOTAL_CREDITS_PD : integer := 32; 00193 VC0_TOTAL_CREDITS_PH : integer := 32; 00194 VC0_TX_LASTPACKET : integer := 28; 00195 00196 VENDOR_ID : bit_vector := X"4953"; 00197 VSEC_BASE_PTR : bit_vector := X"0"; 00198 VSEC_CAP_NEXTPTR : bit_vector := X"000"; 00199 VSEC_CAP_ON : boolean := FALSE; 00200 00201 AER_BASE_PTR : bit_vector := X"128"; 00202 AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE; 00203 AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE; 00204 AER_CAP_ID : bit_vector := X"0001"; 00205 AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0a"; 00206 AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15"; 00207 AER_CAP_NEXTPTR : bit_vector := X"160"; 00208 AER_CAP_ON : boolean := FALSE; 00209 AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE; 00210 AER_CAP_VERSION : bit_vector := X"1"; 00211 00212 CAPABILITIES_PTR : bit_vector := X"40"; 00213 CRM_MODULE_RSTS : bit_vector := X"00"; 00214 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE; 00215 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE; 00216 DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE; 00217 DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE; 00218 DEV_CAP_RSVD_14_12 : integer := 0; 00219 DEV_CAP_RSVD_17_16 : integer := 0; 00220 DEV_CAP_RSVD_31_29 : integer := 0; 00221 DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE; 00222 00223 DISABLE_ASPM_L1_TIMER : boolean := FALSE; 00224 DISABLE_BAR_FILTERING : boolean := FALSE; 00225 DISABLE_ID_CHECK : boolean := FALSE; 00226 DISABLE_RX_TC_FILTER : boolean := FALSE; 00227 DNSTREAM_LINK_NUM : bit_vector := X"00"; 00228 00229 DSN_CAP_ID : bit_vector := X"0003"; 00230 DSN_CAP_VERSION : bit_vector := X"1"; 00231 ENTER_RVRY_EI_L0 : boolean := TRUE; 00232 INFER_EI : bit_vector := X"0c"; 00233 IS_SWITCH : boolean := FALSE; 00234 00235 LAST_CONFIG_DWORD : bit_vector := X"3FF"; 00236 LINK_CAP_ASPM_SUPPORT : integer := 1; 00237 LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE; 00238 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7; 00239 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7; 00240 LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7; 00241 LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7; 00242 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7; 00243 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7; 00244 LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7; 00245 LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7; 00246 LINK_CAP_RSVD_23_22 : integer := 0; 00247 LINK_CONTROL_RCB : integer := 0; 00248 00249 MSI_BASE_PTR : bit_vector := X"48"; 00250 MSI_CAP_ID : bit_vector := X"05"; 00251 MSI_CAP_NEXTPTR : bit_vector := X"60"; 00252 MSIX_BASE_PTR : bit_vector := X"9c"; 00253 MSIX_CAP_ID : bit_vector := X"11"; 00254 MSIX_CAP_NEXTPTR : bit_vector := X"00"; 00255 N_FTS_COMCLK_GEN1 : integer := 255; 00256 N_FTS_COMCLK_GEN2 : integer := 254; 00257 N_FTS_GEN1 : integer := 255; 00258 N_FTS_GEN2 : integer := 255; 00259 00260 PCIE_BASE_PTR : bit_vector := X"60"; 00261 PCIE_CAP_CAPABILITY_ID : bit_vector := X"10"; 00262 PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2"; 00263 PCIE_CAP_ON : boolean := TRUE; 00264 PCIE_CAP_RSVD_15_14 : integer := 0; 00265 PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE; 00266 PCIE_REVISION : integer := 2; 00267 PGL0_LANE : integer := 0; 00268 PGL1_LANE : integer := 1; 00269 PGL2_LANE : integer := 2; 00270 PGL3_LANE : integer := 3; 00271 PGL4_LANE : integer := 4; 00272 PGL5_LANE : integer := 5; 00273 PGL6_LANE : integer := 6; 00274 PGL7_LANE : integer := 7; 00275 PL_AUTO_CONFIG : integer := 0; 00276 PL_FAST_TRAIN : boolean := FALSE; 00277 00278 PM_BASE_PTR : bit_vector := X"40"; 00279 PM_CAP_AUXCURRENT : integer := 0; 00280 PM_CAP_ID : bit_vector := X"01"; 00281 PM_CAP_ON : boolean := TRUE; 00282 PM_CAP_PME_CLOCK : boolean := FALSE; 00283 PM_CAP_RSVD_04 : integer := 0; 00284 PM_CAP_VERSION : integer := 3; 00285 PM_CSR_BPCCEN : boolean := FALSE; 00286 PM_CSR_B2B3 : boolean := FALSE; 00287 00288 RECRC_CHK : integer := 0; 00289 RECRC_CHK_TRIM : boolean := FALSE; 00290 ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE; 00291 SELECT_DLL_IF : boolean := FALSE; 00292 SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE; 00293 SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE; 00294 SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE; 00295 SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE; 00296 SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE; 00297 SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE; 00298 SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE; 00299 SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000"; 00300 SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE; 00301 SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE; 00302 SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0; 00303 SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00"; 00304 SPARE_BIT1 : integer := 0; 00305 SPARE_BIT2 : integer := 0; 00306 SPARE_BIT3 : integer := 0; 00307 SPARE_BIT4 : integer := 0; 00308 SPARE_BIT5 : integer := 0; 00309 SPARE_BIT6 : integer := 0; 00310 SPARE_BIT7 : integer := 0; 00311 SPARE_BIT8 : integer := 0; 00312 SPARE_BYTE0 : bit_vector := X"00"; 00313 SPARE_BYTE1 : bit_vector := X"00"; 00314 SPARE_BYTE2 : bit_vector := X"00"; 00315 SPARE_BYTE3 : bit_vector := X"00"; 00316 SPARE_WORD0 : bit_vector := X"00000000"; 00317 SPARE_WORD1 : bit_vector := X"00000000"; 00318 SPARE_WORD2 : bit_vector := X"00000000"; 00319 SPARE_WORD3 : bit_vector := X"00000000"; 00320 00321 TL_RBYPASS : boolean := FALSE; 00322 TL_TFC_DISABLE : boolean := FALSE; 00323 TL_TX_CHECKS_DISABLE : boolean := FALSE; 00324 EXIT_LOOPBACK_ON_EI : boolean := TRUE; 00325 UPSTREAM_FACING : boolean := TRUE; 00326 UR_INV_REQ : boolean := TRUE; 00327 00328 VC_CAP_ID : bit_vector := X"0002"; 00329 VC_CAP_VERSION : bit_vector := X"1"; 00330 VSEC_CAP_HDR_ID : bit_vector := X"1234"; 00331 VSEC_CAP_HDR_LENGTH : bit_vector := X"018"; 00332 VSEC_CAP_HDR_REVISION : bit_vector := X"1"; 00333 VSEC_CAP_ID : bit_vector := X"000b"; 00334 VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE; 00335 VSEC_CAP_VERSION : bit_vector := X"1" 00336 ); 00337 port ( 00338 --------------------------------------------------------- 00339 -- 1. PCI Express (pci_exp) Interface 00340 --------------------------------------------------------- 00341 00342 -- Tx 00343 pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00344 pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00345 00346 -- Rx 00347 pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00348 pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0); 00349 00350 --------------------------------------------------------- 00351 -- 2. Transaction (TRN) Interface 00352 --------------------------------------------------------- 00353 00354 -- Common 00355 user_clk_out : out std_logic; 00356 user_reset_out : out std_logic; 00357 user_lnk_up : out std_logic; 00358 00359 -- Tx 00360 tx_buf_av : out std_logic_vector(5 downto 0); 00361 tx_cfg_req : out std_logic; 00362 tx_err_drop : out std_logic; 00363 00364 -- s_axis_tx_tready : out std_logic; 00365 -- s_axis_tx_tdata : in std_logic_vector(63 downto 0); 00366 -- s_axis_tx_tstrb : in std_logic_vector(7 downto 0); 00367 -- s_axis_tx_tuser : in std_logic_vector(3 downto 0); 00368 -- s_axis_tx_tlast : in std_logic; 00369 -- s_axis_tx_tvalid : in std_logic; 00370 00371 tx_cfg_gnt : in std_logic; 00372 00373 -- Rx 00374 -- m_axis_rx_tdata : out std_logic_vector(63 downto 0); 00375 -- m_axis_rx_tstrb : out std_logic_vector(7 downto 0); 00376 -- m_axis_rx_tlast : out std_logic; 00377 -- m_axis_rx_tvalid : out std_logic; 00378 -- m_axis_rx_tuser : out std_logic_vector(21 downto 0); 00379 -- m_axis_rx_tready : in std_logic; 00380 rx_np_ok : in std_logic; 00381 00382 00383 -- TRN TX 00384 ------------- 00385 trn_td : in STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS=>'0'); 00386 trn_tsof : in STD_LOGIC := '0'; 00387 trn_teof : in STD_LOGIC := '0'; 00388 trn_tsrc_rdy : in STD_LOGIC := '0'; 00389 trn_tdst_rdy : out STD_LOGIC := '0'; 00390 trn_tsrc_dsc : in STD_LOGIC := '0'; 00391 trn_trem : in STD_LOGIC_VECTOR( 0 DOWNTO 0) := (OTHERS=>'0'); 00392 trn_terrfwd : in STD_LOGIC := '0'; 00393 trn_tstr : in STD_LOGIC := '0'; 00394 trn_tbuf_av : out STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS=>'0'); 00395 trn_tecrc_gen : in STD_LOGIC := '0'; 00396 00397 -- TRN RX 00398 ------------- 00399 trn_rd : out STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS=>'0'); 00400 trn_rsof : out STD_LOGIC := '0'; 00401 trn_reof : out STD_LOGIC := '0'; 00402 trn_rsrc_rdy : out STD_LOGIC := '0'; 00403 trn_rdst_rdy : in STD_LOGIC := '0'; 00404 trn_rsrc_dsc : out STD_LOGIC := '0'; 00405 trn_rrem : out STD_LOGIC_VECTOR( 0 DOWNTO 0) := (OTHERS=>'0'); 00406 trn_rerrfwd : out STD_LOGIC := '0'; 00407 trn_rbar_hit : out STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0'); 00408 trn_recrc_err : out STD_LOGIC := '0'; 00409 00410 00411 -- Flow Control 00412 fc_cpld : out std_logic_vector(11 downto 0); 00413 fc_cplh : out std_logic_vector(7 downto 0); 00414 fc_npd : out std_logic_vector(11 downto 0); 00415 fc_nph : out std_logic_vector(7 downto 0); 00416 fc_pd : out std_logic_vector(11 downto 0); 00417 fc_ph : out std_logic_vector(7 downto 0); 00418 fc_sel : in std_logic_vector(2 downto 0); 00419 00420 --------------------------------------------------------- 00421 -- 3. Configuration (CFG) Interface 00422 --------------------------------------------------------- 00423 00424 cfg_do : out std_logic_vector(31 downto 0); 00425 cfg_rd_wr_done : out std_logic; 00426 cfg_di : in std_logic_vector(31 downto 0); 00427 cfg_byte_en : in std_logic_vector(3 downto 0); 00428 cfg_dwaddr : in std_logic_vector(9 downto 0); 00429 cfg_wr_en : in std_logic; 00430 cfg_rd_en : in std_logic; 00431 00432 cfg_err_cor : in std_logic; 00433 cfg_err_ur : in std_logic; 00434 cfg_err_ecrc : in std_logic; 00435 cfg_err_cpl_timeout : in std_logic; 00436 cfg_err_cpl_abort : in std_logic; 00437 cfg_err_cpl_unexpect : in std_logic; 00438 cfg_err_posted : in std_logic; 00439 cfg_err_locked : in std_logic; 00440 cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0); 00441 cfg_err_cpl_rdy : out std_logic; 00442 cfg_interrupt : in std_logic; 00443 cfg_interrupt_rdy : out std_logic; 00444 cfg_interrupt_assert : in std_logic; 00445 cfg_interrupt_di : in std_logic_vector(7 downto 0); 00446 cfg_interrupt_do : out std_logic_vector(7 downto 0); 00447 cfg_interrupt_mmenable : out std_logic_vector(2 downto 0); 00448 cfg_interrupt_msienable : out std_logic; 00449 cfg_interrupt_msixenable : out std_logic; 00450 cfg_interrupt_msixfm : out std_logic; 00451 cfg_turnoff_ok : in std_logic; 00452 cfg_to_turnoff : out std_logic; 00453 cfg_trn_pending : in std_logic; 00454 cfg_pm_wake : in std_logic; 00455 cfg_bus_number : out std_logic_vector(7 downto 0); 00456 cfg_device_number : out std_logic_vector(4 downto 0); 00457 cfg_function_number : out std_logic_vector(2 downto 0); 00458 cfg_status : out std_logic_vector(15 downto 0); 00459 cfg_command : out std_logic_vector(15 downto 0); 00460 cfg_dstatus : out std_logic_vector(15 downto 0); 00461 cfg_dcommand : out std_logic_vector(15 downto 0); 00462 cfg_lstatus : out std_logic_vector(15 downto 0); 00463 cfg_lcommand : out std_logic_vector(15 downto 0); 00464 cfg_dcommand2 : out std_logic_vector(15 downto 0); 00465 cfg_pcie_link_state : out std_logic_vector(2 downto 0); 00466 cfg_dsn : in std_logic_vector(63 downto 0); 00467 cfg_pmcsr_pme_en : out std_logic; 00468 cfg_pmcsr_pme_status : out std_logic; 00469 cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0); 00470 00471 --------------------------------------------------------- 00472 -- 4. Physical Layer Control and Status (PL) Interface 00473 --------------------------------------------------------- 00474 00475 pl_initial_link_width : out std_logic_vector(2 downto 0); 00476 pl_lane_reversal_mode : out std_logic_vector(1 downto 0); 00477 pl_link_gen2_capable : out std_logic; 00478 pl_link_partner_gen2_supported : out std_logic; 00479 pl_link_upcfg_capable : out std_logic; 00480 pl_ltssm_state : out std_logic_vector(5 downto 0); 00481 pl_received_hot_rst : out std_logic; 00482 pl_sel_link_rate : out std_logic; 00483 pl_sel_link_width : out std_logic_vector(1 downto 0); 00484 pl_directed_link_auton : in std_logic; 00485 pl_directed_link_change : in std_logic_vector(1 downto 0); 00486 pl_directed_link_speed : in std_logic; 00487 pl_directed_link_width : in std_logic_vector(1 downto 0); 00488 pl_upstream_prefer_deemph : in std_logic; 00489 00490 --------------------------------------------------------- 00491 -- 5. System (SYS) Interface 00492 --------------------------------------------------------- 00493 00494 sys_clk : in std_logic; 00495 sys_reset : in std_logic 00496 ); 00497 end cl_v6pcie_m1; 00498 00499 architecture v6_pcie of cl_v6pcie_m1 is 00500 00501 attribute CORE_GENERATION_INFO : string; 00502 attribute CORE_GENERATION_INFO of v6_pcie : ARCHITECTURE is 00503 "cl_v6pcie_m1,v6_pcie_v2_3,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=3,REF_CLK_FREQ=0,MSI_CAP_ON=FALSE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=378,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=FALSE,PIPE_PIPELINE_STAGES=0,REVISION_ID=20,VC_CAP_ON=FALSE}"; 00504 00505 component axi_basic_top 00506 generic ( 00507 C_DATA_WIDTH : integer := 32; -- rx/tx interface data width 00508 C_FAMILY : string := "x7"; -- targeted fpga family 00509 C_ROOT_PORT : BOOLEAN := FALSE; -- pcie block is in root port mode 00510 C_PM_PRIORITY : BOOLEAN := FALSE; -- disable tx packet boundary thrtl 00511 TCQ : integer := 1; -- clock to q time 00512 00513 C_REM_WIDTH : integer := 1; -- trem/rrem width 00514 C_STRB_WIDTH : integer := 4 -- tstrb width 00515 ); 00516 port ( 00517 ----------------------------------------------- 00518 -- user design I/O 00519 ----------------------------------------------- 00520 00521 -- AXI TX 00522 ------------- 00523 s_axis_tx_tdata : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00524 s_axis_tx_tvalid : in std_logic := '0'; 00525 s_axis_tx_tready : out std_logic := '0'; 00526 s_axis_tx_tstrb : in std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0'); 00527 s_axis_tx_tlast : in std_logic := '0'; 00528 s_axis_tx_tuser : in std_logic_vector(3 downto 0) := (others=>'0'); 00529 00530 -- AXI RX 00531 ------------- 00532 m_axis_rx_tdata : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00533 m_axis_rx_tvalid : out std_logic := '0'; 00534 m_axis_rx_tready : in std_logic := '0'; 00535 m_axis_rx_tstrb : out std_logic_vector(C_STRB_WIDTH - 1 downto 0) := (others=>'0'); 00536 m_axis_rx_tlast : out std_logic := '0'; 00537 m_axis_rx_tuser : out std_logic_vector(21 downto 0) := (others=>'0'); 00538 00539 -- user misc. 00540 ------------- 00541 user_turnoff_ok : in std_logic := '0'; 00542 user_tcfg_gnt : in std_logic := '0'; 00543 00544 ----------------------------------------------- 00545 -- PCIe block I/O 00546 ----------------------------------------------- 00547 00548 -- TRN TX 00549 ------------- 00550 trn_td : out std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00551 trn_tsof : out std_logic := '0'; 00552 trn_teof : out std_logic := '0'; 00553 trn_tsrc_rdy : out std_logic := '0'; 00554 trn_tdst_rdy : in std_logic := '0'; 00555 trn_tsrc_dsc : out std_logic := '0'; 00556 trn_trem : out std_logic_vector(C_REM_WIDTH - 1 downto 0) := (others=>'0'); 00557 trn_terrfwd : out std_logic := '0'; 00558 trn_tstr : out std_logic := '0'; 00559 trn_tbuf_av : in std_logic_vector(5 downto 0) := (others=>'0'); 00560 trn_tecrc_gen : out std_logic := '0'; 00561 00562 -- TRN RX 00563 ------------- 00564 trn_rd : in std_logic_vector(C_DATA_WIDTH - 1 downto 0) := (others=>'0'); 00565 trn_rsof : in std_logic := '0'; 00566 trn_reof : in std_logic := '0'; 00567 trn_rsrc_rdy : in std_logic := '0'; 00568 trn_rdst_rdy : out std_logic := '0'; 00569 trn_rsrc_dsc : in std_logic := '0'; 00570 trn_rrem : in std_logic_vector(C_REM_WIDTH - 1 downto 0) := (others=>'0'); 00571 trn_rerrfwd : in std_logic := '0'; 00572 trn_rbar_hit : in std_logic_vector(6 downto 0) := (others=>'0'); 00573 trn_recrc_err : in std_logic := '0'; 00574 00575 -- TRN misc. 00576 ------------- 00577 trn_tcfg_req : in std_logic := '0'; 00578 trn_tcfg_gnt : out std_logic := '0'; 00579 trn_lnk_up : in std_logic := '0'; 00580 00581 -- 7 series/Virtex6 PM 00582 ------------- 00583 cfg_pcie_link_state : in std_logic_vector(2 downto 0) := (others=>'0'); 00584 00585 -- Virtex6 PM 00586 ------------- 00587 cfg_pm_send_pme_to : in std_logic := '0'; 00588 cfg_pmcsr_powerstate : in std_logic_vector(1 downto 0) := (others=>'0'); 00589 trn_rdllp_data : in std_logic_vector(31 downto 0) := (others=>'0'); 00590 trn_rdllp_src_rdy : in std_logic := '0'; 00591 00592 -- Virtex6/Spartan6 PM 00593 ------------- 00594 cfg_to_turnoff : in std_logic := '0'; 00595 cfg_turnoff_ok : out std_logic := '0'; 00596 00597 np_counter : out std_logic_vector(2 downto 0) := (others=>'0'); 00598 user_clk : in std_logic := '0'; 00599 user_rst : in std_logic := '0' 00600 ); 00601 end component; 00602 00603 component pcie_reset_delay_v6 00604 generic ( 00605 PL_FAST_TRAIN : boolean; 00606 REF_CLK_FREQ : integer); 00607 port ( 00608 ref_clk : in std_logic; 00609 sys_reset_n : in std_logic; 00610 delayed_sys_reset_n : out std_logic); 00611 end component; 00612 00613 component pcie_clocking_v6 00614 generic ( 00615 CAP_LINK_WIDTH : integer; 00616 CAP_LINK_SPEED : integer; 00617 REF_CLK_FREQ : integer; 00618 USER_CLK_FREQ : integer); 00619 port ( 00620 sys_clk : in std_logic; 00621 gt_pll_lock : in std_logic; 00622 sel_lnk_rate : in std_logic; 00623 sel_lnk_width : in std_logic_vector(1 downto 0); 00624 sys_clk_bufg : out std_logic; 00625 pipe_clk : out std_logic; 00626 user_clk : out std_logic; 00627 block_clk : out std_logic; 00628 drp_clk : out std_logic; 00629 clock_locked : out std_logic); 00630 end component; 00631 00632 component pcie_2_0_v6 00633 generic ( 00634 REF_CLK_FREQ : integer; 00635 PIPE_PIPELINE_STAGES : integer; 00636 LINK_CAP_MAX_LINK_WIDTH_int : integer; 00637 AER_BASE_PTR : bit_vector; 00638 AER_CAP_ECRC_CHECK_CAPABLE : boolean; 00639 AER_CAP_ECRC_GEN_CAPABLE : boolean; 00640 AER_CAP_ID : bit_vector; 00641 AER_CAP_INT_MSG_NUM_MSI : bit_vector; 00642 AER_CAP_INT_MSG_NUM_MSIX : bit_vector; 00643 AER_CAP_NEXTPTR : bit_vector; 00644 AER_CAP_ON : boolean; 00645 AER_CAP_PERMIT_ROOTERR_UPDATE : boolean; 00646 AER_CAP_VERSION : bit_vector; 00647 ALLOW_X8_GEN2 : boolean; 00648 BAR0 : bit_vector; 00649 BAR1 : bit_vector; 00650 BAR2 : bit_vector; 00651 BAR3 : bit_vector; 00652 BAR4 : bit_vector; 00653 BAR5 : bit_vector; 00654 CAPABILITIES_PTR : bit_vector; 00655 CARDBUS_CIS_POINTER : bit_vector; 00656 CLASS_CODE : bit_vector; 00657 CMD_INTX_IMPLEMENTED : boolean; 00658 CPL_TIMEOUT_DISABLE_SUPPORTED : boolean; 00659 CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector; 00660 CRM_MODULE_RSTS : bit_vector; 00661 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean; 00662 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean; 00663 DEV_CAP_ENDPOINT_L0S_LATENCY : integer; 00664 DEV_CAP_ENDPOINT_L1_LATENCY : integer; 00665 DEV_CAP_EXT_TAG_SUPPORTED : boolean; 00666 DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean; 00667 DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer; 00668 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer; 00669 DEV_CAP_ROLE_BASED_ERROR : boolean; 00670 DEV_CAP_RSVD_14_12 : integer; 00671 DEV_CAP_RSVD_17_16 : integer; 00672 DEV_CAP_RSVD_31_29 : integer; 00673 DEV_CONTROL_AUX_POWER_SUPPORTED : boolean; 00674 DEVICE_ID : bit_vector; 00675 DISABLE_ASPM_L1_TIMER : boolean; 00676 DISABLE_BAR_FILTERING : boolean; 00677 DISABLE_ID_CHECK : boolean; 00678 DISABLE_LANE_REVERSAL : boolean; 00679 DISABLE_RX_TC_FILTER : boolean; 00680 DISABLE_SCRAMBLING : boolean; 00681 DNSTREAM_LINK_NUM : bit_vector; 00682 DSN_BASE_PTR : bit_vector; 00683 DSN_CAP_ID : bit_vector; 00684 DSN_CAP_NEXTPTR : bit_vector; 00685 DSN_CAP_ON : boolean; 00686 DSN_CAP_VERSION : bit_vector; 00687 ENABLE_MSG_ROUTE : bit_vector; 00688 ENABLE_RX_TD_ECRC_TRIM : boolean; 00689 ENTER_RVRY_EI_L0 : boolean; 00690 EXPANSION_ROM : bit_vector; 00691 EXT_CFG_CAP_PTR : bit_vector; 00692 EXT_CFG_XP_CAP_PTR : bit_vector; 00693 HEADER_TYPE : bit_vector; 00694 INFER_EI : bit_vector; 00695 INTERRUPT_PIN : bit_vector; 00696 IS_SWITCH : boolean; 00697 LAST_CONFIG_DWORD : bit_vector; 00698 LINK_CAP_ASPM_SUPPORT : integer; 00699 LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean; 00700 LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean; 00701 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer; 00702 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer; 00703 LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer; 00704 LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer; 00705 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer; 00706 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer; 00707 LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer; 00708 LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer; 00709 LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean; 00710 LINK_CAP_MAX_LINK_SPEED : bit_vector; 00711 LINK_CAP_MAX_LINK_WIDTH : bit_vector; 00712 LINK_CAP_RSVD_23_22 : integer; 00713 LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean; 00714 LINK_CONTROL_RCB : integer; 00715 LINK_CTRL2_DEEMPHASIS : boolean; 00716 LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean; 00717 LINK_CTRL2_TARGET_LINK_SPEED : bit_vector; 00718 LINK_STATUS_SLOT_CLOCK_CONFIG : boolean; 00719 LL_ACK_TIMEOUT : bit_vector; 00720 LL_ACK_TIMEOUT_EN : boolean; 00721 LL_ACK_TIMEOUT_FUNC : integer; 00722 LL_REPLAY_TIMEOUT : bit_vector; 00723 LL_REPLAY_TIMEOUT_EN : boolean; 00724 LL_REPLAY_TIMEOUT_FUNC : integer; 00725 LTSSM_MAX_LINK_WIDTH : bit_vector; 00726 MSI_BASE_PTR : bit_vector; 00727 MSI_CAP_ID : bit_vector; 00728 MSI_CAP_MULTIMSGCAP : integer; 00729 MSI_CAP_MULTIMSG_EXTENSION : integer; 00730 MSI_CAP_NEXTPTR : bit_vector; 00731 MSI_CAP_ON : boolean; 00732 MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean; 00733 MSI_CAP_64_BIT_ADDR_CAPABLE : boolean; 00734 MSIX_BASE_PTR : bit_vector; 00735 MSIX_CAP_ID : bit_vector; 00736 MSIX_CAP_NEXTPTR : bit_vector; 00737 MSIX_CAP_ON : boolean; 00738 MSIX_CAP_PBA_BIR : integer; 00739 MSIX_CAP_PBA_OFFSET : bit_vector; 00740 MSIX_CAP_TABLE_BIR : integer; 00741 MSIX_CAP_TABLE_OFFSET : bit_vector; 00742 MSIX_CAP_TABLE_SIZE : bit_vector; 00743 N_FTS_COMCLK_GEN1 : integer; 00744 N_FTS_COMCLK_GEN2 : integer; 00745 N_FTS_GEN1 : integer; 00746 N_FTS_GEN2 : integer; 00747 PCIE_BASE_PTR : bit_vector; 00748 PCIE_CAP_CAPABILITY_ID : bit_vector; 00749 PCIE_CAP_CAPABILITY_VERSION : bit_vector; 00750 PCIE_CAP_DEVICE_PORT_TYPE : bit_vector; 00751 PCIE_CAP_INT_MSG_NUM : bit_vector; 00752 PCIE_CAP_NEXTPTR : bit_vector; 00753 PCIE_CAP_ON : boolean; 00754 PCIE_CAP_RSVD_15_14 : integer; 00755 PCIE_CAP_SLOT_IMPLEMENTED : boolean; 00756 PCIE_REVISION : integer; 00757 PGL0_LANE : integer; 00758 PGL1_LANE : integer; 00759 PGL2_LANE : integer; 00760 PGL3_LANE : integer; 00761 PGL4_LANE : integer; 00762 PGL5_LANE : integer; 00763 PGL6_LANE : integer; 00764 PGL7_LANE : integer; 00765 PL_AUTO_CONFIG : integer; 00766 PL_FAST_TRAIN : boolean; 00767 PM_BASE_PTR : bit_vector; 00768 PM_CAP_AUXCURRENT : integer; 00769 PM_CAP_DSI : boolean; 00770 PM_CAP_D1SUPPORT : boolean; 00771 PM_CAP_D2SUPPORT : boolean; 00772 PM_CAP_ID : bit_vector; 00773 PM_CAP_NEXTPTR : bit_vector; 00774 PM_CAP_ON : boolean; 00775 PM_CAP_PME_CLOCK : boolean; 00776 PM_CAP_PMESUPPORT : bit_vector; 00777 PM_CAP_RSVD_04 : integer; 00778 PM_CAP_VERSION : integer; 00779 PM_CSR_BPCCEN : boolean; 00780 PM_CSR_B2B3 : boolean; 00781 PM_CSR_NOSOFTRST : boolean; 00782 PM_DATA0 : bit_vector; 00783 PM_DATA1 : bit_vector; 00784 PM_DATA2 : bit_vector; 00785 PM_DATA3 : bit_vector; 00786 PM_DATA4 : bit_vector; 00787 PM_DATA5 : bit_vector; 00788 PM_DATA6 : bit_vector; 00789 PM_DATA7 : bit_vector; 00790 PM_DATA_SCALE0 : bit_vector; 00791 PM_DATA_SCALE1 : bit_vector; 00792 PM_DATA_SCALE2 : bit_vector; 00793 PM_DATA_SCALE3 : bit_vector; 00794 PM_DATA_SCALE4 : bit_vector; 00795 PM_DATA_SCALE5 : bit_vector; 00796 PM_DATA_SCALE6 : bit_vector; 00797 PM_DATA_SCALE7 : bit_vector; 00798 RECRC_CHK : integer; 00799 RECRC_CHK_TRIM : boolean; 00800 REVISION_ID : bit_vector; 00801 ROOT_CAP_CRS_SW_VISIBILITY : boolean; 00802 SELECT_DLL_IF : boolean; 00803 SLOT_CAP_ATT_BUTTON_PRESENT : boolean; 00804 SLOT_CAP_ATT_INDICATOR_PRESENT : boolean; 00805 SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean; 00806 SLOT_CAP_HOTPLUG_CAPABLE : boolean; 00807 SLOT_CAP_HOTPLUG_SURPRISE : boolean; 00808 SLOT_CAP_MRL_SENSOR_PRESENT : boolean; 00809 SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean; 00810 SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector; 00811 SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean; 00812 SLOT_CAP_POWER_INDICATOR_PRESENT : boolean; 00813 SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer; 00814 SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector; 00815 SPARE_BIT0 : integer; 00816 SPARE_BIT1 : integer; 00817 SPARE_BIT2 : integer; 00818 SPARE_BIT3 : integer; 00819 SPARE_BIT4 : integer; 00820 SPARE_BIT5 : integer; 00821 SPARE_BIT6 : integer; 00822 SPARE_BIT7 : integer; 00823 SPARE_BIT8 : integer; 00824 SPARE_BYTE0 : bit_vector; 00825 SPARE_BYTE1 : bit_vector; 00826 SPARE_BYTE2 : bit_vector; 00827 SPARE_BYTE3 : bit_vector; 00828 SPARE_WORD0 : bit_vector; 00829 SPARE_WORD1 : bit_vector; 00830 SPARE_WORD2 : bit_vector; 00831 SPARE_WORD3 : bit_vector; 00832 SUBSYSTEM_ID : bit_vector; 00833 SUBSYSTEM_VENDOR_ID : bit_vector; 00834 TL_RBYPASS : boolean; 00835 TL_RX_RAM_RADDR_LATENCY : integer; 00836 TL_RX_RAM_RDATA_LATENCY : integer; 00837 TL_RX_RAM_WRITE_LATENCY : integer; 00838 TL_TFC_DISABLE : boolean; 00839 TL_TX_CHECKS_DISABLE : boolean; 00840 TL_TX_RAM_RADDR_LATENCY : integer; 00841 TL_TX_RAM_RDATA_LATENCY : integer; 00842 TL_TX_RAM_WRITE_LATENCY : integer; 00843 UPCONFIG_CAPABLE : boolean; 00844 UPSTREAM_FACING : boolean; 00845 UR_INV_REQ : boolean; 00846 USER_CLK_FREQ : integer; 00847 EXIT_LOOPBACK_ON_EI : boolean; 00848 VC_BASE_PTR : bit_vector; 00849 VC_CAP_ID : bit_vector; 00850 VC_CAP_NEXTPTR : bit_vector; 00851 VC_CAP_ON : boolean; 00852 VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean; 00853 VC_CAP_VERSION : bit_vector; 00854 VC0_CPL_INFINITE : boolean; 00855 VC0_RX_RAM_LIMIT : bit_vector; 00856 VC0_TOTAL_CREDITS_CD : integer; 00857 VC0_TOTAL_CREDITS_CH : integer; 00858 VC0_TOTAL_CREDITS_NPH : integer; 00859 VC0_TOTAL_CREDITS_PD : integer; 00860 VC0_TOTAL_CREDITS_PH : integer; 00861 VC0_TX_LASTPACKET : integer; 00862 VENDOR_ID : bit_vector; 00863 VSEC_BASE_PTR : bit_vector; 00864 VSEC_CAP_HDR_ID : bit_vector; 00865 VSEC_CAP_HDR_LENGTH : bit_vector; 00866 VSEC_CAP_HDR_REVISION : bit_vector; 00867 VSEC_CAP_ID : bit_vector; 00868 VSEC_CAP_IS_LINK_VISIBLE : boolean; 00869 VSEC_CAP_NEXTPTR : bit_vector; 00870 VSEC_CAP_ON : boolean; 00871 VSEC_CAP_VERSION : bit_vector); 00872 port ( 00873 PCIEXPRXN : in std_logic_vector(3 downto 0); 00874 PCIEXPRXP : in std_logic_vector(3 downto 0); 00875 PCIEXPTXN : out std_logic_vector(3 downto 0); 00876 PCIEXPTXP : out std_logic_vector(3 downto 0); 00877 SYSCLK : in std_logic; 00878 FUNDRSTN : in std_logic; 00879 TRNLNKUPN : out std_logic; 00880 PHYRDYN : out std_logic; 00881 USERRSTN : out std_logic; 00882 RECEIVEDFUNCLVLRSTN : out std_logic; 00883 LNKCLKEN : out std_logic; 00884 SYSRSTN : in std_logic; 00885 PLRSTN : in std_logic; 00886 DLRSTN : in std_logic; 00887 TLRSTN : in std_logic; 00888 FUNCLVLRSTN : in std_logic; 00889 CMRSTN : in std_logic; 00890 CMSTICKYRSTN : in std_logic; 00891 TRNRBARHITN : out std_logic_vector(6 downto 0); 00892 TRNRD : out std_logic_vector(63 downto 0); 00893 TRNRECRCERRN : out std_logic; 00894 TRNREOFN : out std_logic; 00895 TRNRERRFWDN : out std_logic; 00896 TRNRREMN : out std_logic; 00897 TRNRSOFN : out std_logic; 00898 TRNRSRCDSCN : out std_logic; 00899 TRNRSRCRDYN : out std_logic; 00900 TRNRDSTRDYN : in std_logic; 00901 TRNRNPOKN : in std_logic; 00902 TRNRDLLPDATA : out std_logic_vector(31 downto 0); 00903 TRNRDLLPSRCRDYN : out std_logic; 00904 TRNTBUFAV : out std_logic_vector(5 downto 0); 00905 TRNTCFGREQN : out std_logic; 00906 TRNTDLLPDSTRDYN : out std_logic; 00907 TRNTDSTRDYN : out std_logic; 00908 TRNTERRDROPN : out std_logic; 00909 TRNTCFGGNTN : in std_logic; 00910 TRNTD : in std_logic_vector(63 downto 0); 00911 TRNTDLLPDATA : in std_logic_vector(31 downto 0); 00912 TRNTDLLPSRCRDYN : in std_logic; 00913 TRNTECRCGENN : in std_logic; 00914 TRNTEOFN : in std_logic; 00915 TRNTERRFWDN : in std_logic; 00916 TRNTREMN : in std_logic; 00917 TRNTSOFN : in std_logic; 00918 TRNTSRCDSCN : in std_logic; 00919 TRNTSRCRDYN : in std_logic; 00920 TRNTSTRN : in std_logic; 00921 TRNFCCPLD : out std_logic_vector(11 downto 0); 00922 TRNFCCPLH : out std_logic_vector(7 downto 0); 00923 TRNFCNPD : out std_logic_vector(11 downto 0); 00924 TRNFCNPH : out std_logic_vector(7 downto 0); 00925 TRNFCPD : out std_logic_vector(11 downto 0); 00926 TRNFCPH : out std_logic_vector(7 downto 0); 00927 TRNFCSEL : in std_logic_vector(2 downto 0); 00928 CFGAERECRCCHECKEN : out std_logic; 00929 CFGAERECRCGENEN : out std_logic; 00930 CFGCOMMANDBUSMASTERENABLE : out std_logic; 00931 CFGCOMMANDINTERRUPTDISABLE : out std_logic; 00932 CFGCOMMANDIOENABLE : out std_logic; 00933 CFGCOMMANDMEMENABLE : out std_logic; 00934 CFGCOMMANDSERREN : out std_logic; 00935 CFGDEVCONTROLAUXPOWEREN : out std_logic; 00936 CFGDEVCONTROLCORRERRREPORTINGEN : out std_logic; 00937 CFGDEVCONTROLENABLERO : out std_logic; 00938 CFGDEVCONTROLEXTTAGEN : out std_logic; 00939 CFGDEVCONTROLFATALERRREPORTINGEN : out std_logic; 00940 CFGDEVCONTROLMAXPAYLOAD : out std_logic_vector(2 downto 0); 00941 CFGDEVCONTROLMAXREADREQ : out std_logic_vector(2 downto 0); 00942 CFGDEVCONTROLNONFATALREPORTINGEN : out std_logic; 00943 CFGDEVCONTROLNOSNOOPEN : out std_logic; 00944 CFGDEVCONTROLPHANTOMEN : out std_logic; 00945 CFGDEVCONTROLURERRREPORTINGEN : out std_logic; 00946 CFGDEVCONTROL2CPLTIMEOUTDIS : out std_logic; 00947 CFGDEVCONTROL2CPLTIMEOUTVAL : out std_logic_vector(3 downto 0); 00948 CFGDEVSTATUSCORRERRDETECTED : out std_logic; 00949 CFGDEVSTATUSFATALERRDETECTED : out std_logic; 00950 CFGDEVSTATUSNONFATALERRDETECTED : out std_logic; 00951 CFGDEVSTATUSURDETECTED : out std_logic; 00952 CFGDO : out std_logic_vector(31 downto 0); 00953 CFGERRAERHEADERLOGSETN : out std_logic; 00954 CFGERRCPLRDYN : out std_logic; 00955 CFGINTERRUPTDO : out std_logic_vector(7 downto 0); 00956 CFGINTERRUPTMMENABLE : out std_logic_vector(2 downto 0); 00957 CFGINTERRUPTMSIENABLE : out std_logic; 00958 CFGINTERRUPTMSIXENABLE : out std_logic; 00959 CFGINTERRUPTMSIXFM : out std_logic; 00960 CFGINTERRUPTRDYN : out std_logic; 00961 CFGLINKCONTROLRCB : out std_logic; 00962 CFGLINKCONTROLASPMCONTROL : out std_logic_vector(1 downto 0); 00963 CFGLINKCONTROLAUTOBANDWIDTHINTEN : out std_logic; 00964 CFGLINKCONTROLBANDWIDTHINTEN : out std_logic; 00965 CFGLINKCONTROLCLOCKPMEN : out std_logic; 00966 CFGLINKCONTROLCOMMONCLOCK : out std_logic; 00967 CFGLINKCONTROLEXTENDEDSYNC : out std_logic; 00968 CFGLINKCONTROLHWAUTOWIDTHDIS : out std_logic; 00969 CFGLINKCONTROLLINKDISABLE : out std_logic; 00970 CFGLINKCONTROLRETRAINLINK : out std_logic; 00971 CFGLINKSTATUSAUTOBANDWIDTHSTATUS : out std_logic; 00972 CFGLINKSTATUSBANDWITHSTATUS : out std_logic; 00973 CFGLINKSTATUSCURRENTSPEED : out std_logic_vector(1 downto 0); 00974 CFGLINKSTATUSDLLACTIVE : out std_logic; 00975 CFGLINKSTATUSLINKTRAINING : out std_logic; 00976 CFGLINKSTATUSNEGOTIATEDWIDTH : out std_logic_vector(3 downto 0); 00977 CFGMSGDATA : out std_logic_vector(15 downto 0); 00978 CFGMSGRECEIVED : out std_logic; 00979 CFGMSGRECEIVEDASSERTINTA : out std_logic; 00980 CFGMSGRECEIVEDASSERTINTB : out std_logic; 00981 CFGMSGRECEIVEDASSERTINTC : out std_logic; 00982 CFGMSGRECEIVEDASSERTINTD : out std_logic; 00983 CFGMSGRECEIVEDDEASSERTINTA : out std_logic; 00984 CFGMSGRECEIVEDDEASSERTINTB : out std_logic; 00985 CFGMSGRECEIVEDDEASSERTINTC : out std_logic; 00986 CFGMSGRECEIVEDDEASSERTINTD : out std_logic; 00987 CFGMSGRECEIVEDERRCOR : out std_logic; 00988 CFGMSGRECEIVEDERRFATAL : out std_logic; 00989 CFGMSGRECEIVEDERRNONFATAL : out std_logic; 00990 CFGMSGRECEIVEDPMASNAK : out std_logic; 00991 CFGMSGRECEIVEDPMETO : out std_logic; 00992 CFGMSGRECEIVEDPMETOACK : out std_logic; 00993 CFGMSGRECEIVEDPMPME : out std_logic; 00994 CFGMSGRECEIVEDSETSLOTPOWERLIMIT : out std_logic; 00995 CFGMSGRECEIVEDUNLOCK : out std_logic; 00996 CFGPCIELINKSTATE : out std_logic_vector(2 downto 0); 00997 CFGPMCSRPMEEN : out std_logic; 00998 CFGPMCSRPMESTATUS : out std_logic; 00999 CFGPMCSRPOWERSTATE : out std_logic_vector(1 downto 0); 01000 CFGPMRCVASREQL1N : out std_logic; 01001 CFGPMRCVENTERL1N : out std_logic; 01002 CFGPMRCVENTERL23N : out std_logic; 01003 CFGPMRCVREQACKN : out std_logic; 01004 CFGRDWRDONEN : out std_logic; 01005 CFGSLOTCONTROLELECTROMECHILCTLPULSE : out std_logic; 01006 CFGTRANSACTION : out std_logic; 01007 CFGTRANSACTIONADDR : out std_logic_vector(6 downto 0); 01008 CFGTRANSACTIONTYPE : out std_logic; 01009 CFGVCTCVCMAP : out std_logic_vector(6 downto 0); 01010 CFGBYTEENN : in std_logic_vector(3 downto 0); 01011 CFGDI : in std_logic_vector(31 downto 0); 01012 CFGDSBUSNUMBER : in std_logic_vector(7 downto 0); 01013 CFGDSDEVICENUMBER : in std_logic_vector(4 downto 0); 01014 CFGDSFUNCTIONNUMBER : in std_logic_vector(2 downto 0); 01015 CFGDSN : in std_logic_vector(63 downto 0); 01016 CFGDWADDR : in std_logic_vector(9 downto 0); 01017 CFGERRACSN : in std_logic; 01018 CFGERRAERHEADERLOG : in std_logic_vector(127 downto 0); 01019 CFGERRCORN : in std_logic; 01020 CFGERRCPLABORTN : in std_logic; 01021 CFGERRCPLTIMEOUTN : in std_logic; 01022 CFGERRCPLUNEXPECTN : in std_logic; 01023 CFGERRECRCN : in std_logic; 01024 CFGERRLOCKEDN : in std_logic; 01025 CFGERRPOSTEDN : in std_logic; 01026 CFGERRTLPCPLHEADER : in std_logic_vector(47 downto 0); 01027 CFGERRURN : in std_logic; 01028 CFGINTERRUPTASSERTN : in std_logic; 01029 CFGINTERRUPTDI : in std_logic_vector(7 downto 0); 01030 CFGINTERRUPTN : in std_logic; 01031 CFGPMDIRECTASPML1N : in std_logic; 01032 CFGPMSENDPMACKN : in std_logic; 01033 CFGPMSENDPMETON : in std_logic; 01034 CFGPMSENDPMNAKN : in std_logic; 01035 CFGPMTURNOFFOKN : in std_logic; 01036 CFGPMWAKEN : in std_logic; 01037 CFGPORTNUMBER : in std_logic_vector(7 downto 0); 01038 CFGRDENN : in std_logic; 01039 CFGTRNPENDINGN : in std_logic; 01040 CFGWRENN : in std_logic; 01041 CFGWRREADONLYN : in std_logic; 01042 CFGWRRW1CASRWN : in std_logic; 01043 PLINITIALLINKWIDTH : out std_logic_vector(2 downto 0); 01044 PLLANEREVERSALMODE : out std_logic_vector(1 downto 0); 01045 PLLINKGEN2CAP : out std_logic; 01046 PLLINKPARTNERGEN2SUPPORTED : out std_logic; 01047 PLLINKUPCFGCAP : out std_logic; 01048 PLLTSSMSTATE : out std_logic_vector(5 downto 0); 01049 PLPHYLNKUPN : out std_logic; 01050 PLRECEIVEDHOTRST : out std_logic; 01051 PLRXPMSTATE : out std_logic_vector(1 downto 0); 01052 PLSELLNKRATE : out std_logic; 01053 PLSELLNKWIDTH : out std_logic_vector(1 downto 0); 01054 PLTXPMSTATE : out std_logic_vector(2 downto 0); 01055 PLDIRECTEDLINKAUTON : in std_logic; 01056 PLDIRECTEDLINKCHANGE : in std_logic_vector(1 downto 0); 01057 PLDIRECTEDLINKSPEED : in std_logic; 01058 PLDIRECTEDLINKWIDTH : in std_logic_vector(1 downto 0); 01059 PLDOWNSTREAMDEEMPHSOURCE : in std_logic; 01060 PLUPSTREAMPREFERDEEMPH : in std_logic; 01061 PLTRANSMITHOTRST : in std_logic; 01062 DBGSCLRA : out std_logic; 01063 DBGSCLRB : out std_logic; 01064 DBGSCLRC : out std_logic; 01065 DBGSCLRD : out std_logic; 01066 DBGSCLRE : out std_logic; 01067 DBGSCLRF : out std_logic; 01068 DBGSCLRG : out std_logic; 01069 DBGSCLRH : out std_logic; 01070 DBGSCLRI : out std_logic; 01071 DBGSCLRJ : out std_logic; 01072 DBGSCLRK : out std_logic; 01073 DBGVECA : out std_logic_vector(63 downto 0); 01074 DBGVECB : out std_logic_vector(63 downto 0); 01075 DBGVECC : out std_logic_vector(11 downto 0); 01076 PLDBGVEC : out std_logic_vector(11 downto 0); 01077 DBGMODE : in std_logic_vector(1 downto 0); 01078 DBGSUBMODE : in std_logic; 01079 PLDBGMODE : in std_logic_vector(2 downto 0); 01080 PCIEDRPDO : out std_logic_vector(15 downto 0); 01081 PCIEDRPDRDY : out std_logic; 01082 PCIEDRPCLK : in std_logic; 01083 PCIEDRPDADDR : in std_logic_vector(8 downto 0); 01084 PCIEDRPDEN : in std_logic; 01085 PCIEDRPDI : in std_logic_vector(15 downto 0); 01086 PCIEDRPDWE : in std_logic; 01087 GTPLLLOCK : out std_logic; 01088 PIPECLK : in std_logic; 01089 USERCLK : in std_logic; 01090 DRPCLK : in std_logic; 01091 CLOCKLOCKED : in std_logic; 01092 TxOutClk : out std_logic); 01093 end component; 01094 01095 function to_integer ( 01096 val_in : bit_vector) return integer is 01097 01098 constant vctr : bit_vector(val_in'high-val_in'low downto 0) := val_in; 01099 variable ret : integer := 0; 01100 begin 01101 for index in vctr'range loop 01102 if (vctr(index) = '1') then 01103 ret := ret + (2**index); 01104 end if; 01105 end loop; 01106 return(ret); 01107 end to_integer; 01108 01109 function to_stdlogic ( 01110 in_val : in boolean) return std_logic is 01111 begin 01112 if (in_val) then 01113 return('1'); 01114 else 01115 return('0'); 01116 end if; 01117 end to_stdlogic; 01118 01119 function pad_gen ( 01120 in_vec : bit_vector; 01121 op_len : integer) 01122 return bit_vector is 01123 variable ret : bit_vector(op_len-1 downto 0) := (others => '0'); 01124 constant len : integer := in_vec'length; -- length of input vector 01125 begin -- pad_gen 01126 for i in 0 to op_len-1 loop 01127 if (i < len) then 01128 ret(i) := in_vec(len-i-1); 01129 else 01130 ret(i) := '0'; 01131 end if; 01132 end loop; -- i 01133 return ret; 01134 end pad_gen; 01135 01136 constant LINK_CAP_MAX_LINK_SPEED_int : integer := to_integer(LINK_CAP_MAX_LINK_SPEED); 01137 01138 signal rx_func_level_reset_n : std_logic; 01139 signal cfg_msg_received : std_logic; 01140 signal cfg_msg_received_pme_to : std_logic; 01141 01142 signal cfg_cmd_bme : std_logic; 01143 signal cfg_cmd_intdis : std_logic; 01144 signal cfg_cmd_io_en : std_logic; 01145 signal cfg_cmd_mem_en : std_logic; 01146 signal cfg_cmd_serr_en : std_logic; 01147 signal cfg_dev_control_aux_power_en : std_logic; 01148 signal cfg_dev_control_corr_err_reporting_en : std_logic; 01149 signal cfg_dev_control_enable_relaxed_order : std_logic; 01150 signal cfg_dev_control_ext_tag_en : std_logic; 01151 signal cfg_dev_control_fatal_err_reporting_en : std_logic; 01152 signal cfg_dev_control_maxpayload : std_logic_vector(2 downto 0); 01153 signal cfg_dev_control_max_read_req : std_logic_vector(2 downto 0); 01154 signal cfg_dev_control_non_fatal_reporting_en : std_logic; 01155 signal cfg_dev_control_nosnoop_en : std_logic; 01156 signal cfg_dev_control_phantom_en : std_logic; 01157 signal cfg_dev_control_ur_err_reporting_en : std_logic; 01158 signal cfg_dev_control2_cpltimeout_dis : std_logic; 01159 signal cfg_dev_control2_cpltimeout_val : std_logic_vector(3 downto 0); 01160 signal cfg_dev_status_corr_err_detected : std_logic; 01161 signal cfg_dev_status_fatal_err_detected : std_logic; 01162 signal cfg_dev_status_nonfatal_err_detected : std_logic; 01163 signal cfg_dev_status_ur_detected : std_logic; 01164 signal cfg_link_control_auto_bandwidth_int_en : std_logic; 01165 signal cfg_link_control_bandwidth_int_en : std_logic; 01166 signal cfg_link_control_hw_auto_width_dis : std_logic; 01167 signal cfg_link_control_clock_pm_en : std_logic; 01168 signal cfg_link_control_extended_sync : std_logic; 01169 signal cfg_link_control_common_clock : std_logic; 01170 signal cfg_link_control_retrain_link : std_logic; 01171 signal cfg_link_control_linkdisable : std_logic; 01172 signal cfg_link_control_rcb : std_logic; 01173 signal cfg_link_control_aspm_control : std_logic_vector(1 downto 0); 01174 signal cfg_link_status_autobandwidth_status : std_logic; 01175 signal cfg_link_status_bandwidth_status : std_logic; 01176 signal cfg_link_status_dll_active : std_logic; 01177 signal cfg_link_status_link_training : std_logic; 01178 signal cfg_link_status_negotiated_link_width : std_logic_vector(3 downto 0); 01179 signal cfg_link_status_current_speed : std_logic_vector(1 downto 0); 01180 signal cfg_msg_data : std_logic_vector(15 downto 0); 01181 01182 signal sys_reset_n : std_logic; 01183 signal sys_reset_n_d : std_logic; 01184 signal phy_rdy_n : std_logic; 01185 01186 signal TxOutClk : std_logic; 01187 signal TxOutClk_bufg : std_logic; 01188 01189 signal cfg_bus_number_d : std_logic_vector(7 downto 0); 01190 signal cfg_device_number_d : std_logic_vector(4 downto 0); 01191 signal cfg_function_number_d : std_logic_vector(2 downto 0); 01192 01193 signal trn_rdllp_data : std_logic_vector(31 downto 0); 01194 signal trn_rdllp_src_rdy_n : std_logic; 01195 signal trn_rdllp_src_rdy : std_logic; 01196 01197 -- assigns to outputs 01198 01199 signal gt_pll_lock : std_logic; 01200 01201 signal pipe_clk : std_logic; 01202 signal user_clk : std_logic; 01203 signal clock_locked : std_logic; 01204 signal phy_rdy : std_logic; 01205 01206 signal drp_clk : std_logic; 01207 01208 signal trn_reset_n_d : std_logic; 01209 signal sys_reset_d : std_logic; 01210 signal trn_reset_n : std_logic; 01211 signal trn_reset_n_int1 : std_logic; 01212 signal trn_reset_n_1_d : std_logic; 01213 signal trn_lnk_up_n : std_logic; 01214 signal trn_lnk_up_n_1 : std_logic; 01215 signal user_reset_out_int : std_logic; 01216 signal user_lnk_up_int : std_logic; 01217 signal user_lnk_up_d : std_logic; 01218 signal tx_cfg_req_int : std_logic; 01219 signal cfg_pcie_link_state_int : std_logic_vector(2 downto 0); 01220 signal cfg_pmcsr_powerstate_int : std_logic_vector(1 downto 0); 01221 signal cfg_to_turnoff_int : std_logic; 01222 01223 -- Declare intermediate signals for referenced outputs 01224 signal trn_tcfg_req_n : std_logic; 01225 signal trn_tcfg_gnt_n : std_logic; 01226 signal trn_tcfg_gnt : std_logic; 01227 signal trn_terr_drop_n : std_logic; 01228 signal trn_rdst_rdy_n : std_logic; 01229 signal trn_rnp_ok_n : std_logic; 01230 signal trn_tdst_rdy_n : std_logic; 01231 -- signal trn_tdst_rdy : std_logic; 01232 -- signal trn_rd : std_logic_vector(63 downto 0); 01233 signal trn_rrem_n : std_logic; 01234 -- signal trn_rrem : std_logic_vector(0 downto 0); 01235 -- signal trn_td : std_logic_vector(63 downto 0); 01236 signal trn_trem_n : std_logic; 01237 -- signal trn_trem : std_logic_vector(0 downto 0); 01238 signal trn_rsof_n : std_logic; 01239 signal trn_reof_n : std_logic; 01240 signal trn_rsrc_rdy_n : std_logic; 01241 signal trn_rsrc_dsc_n : std_logic; 01242 signal trn_rerrfwd_n : std_logic; 01243 signal trn_rbar_hit_n : std_logic_vector(6 downto 0); 01244 signal trn_recrc_err_n : std_logic; 01245 -- signal trn_rsof : std_logic; 01246 -- signal trn_reof : std_logic; 01247 -- signal trn_rsrc_rdy : std_logic; 01248 -- signal trn_rdst_rdy : std_logic; 01249 -- signal trn_rsrc_dsc : std_logic; 01250 -- signal trn_rerrfwd : std_logic; 01251 -- signal trn_rbar_hit : std_logic_vector(6 downto 0); 01252 -- signal trn_recrc_err : std_logic; 01253 signal trn_tsof_n : std_logic; 01254 signal trn_teof_n : std_logic; 01255 signal trn_tsrc_rdy_n : std_logic; 01256 signal trn_tsrc_dsc_n : std_logic; 01257 signal trn_terrfwd_n : std_logic; 01258 signal trn_tstr_n : std_logic; 01259 -- signal trn_tecrc_gen : std_logic; 01260 -- signal trn_tsof : std_logic; 01261 -- signal trn_teof : std_logic; 01262 -- signal trn_tsrc_rdy : std_logic; 01263 -- signal trn_tsrc_dsc : std_logic; 01264 -- signal trn_terrfwd : std_logic; 01265 -- signal trn_tstr : std_logic; 01266 signal cfg_rd_wr_done_n : std_logic; 01267 signal cfg_err_cpl_rdy_n : std_logic; 01268 signal cfg_interrupt_rdy_n : std_logic; 01269 signal cfg_byte_en_n : std_logic_vector(3 downto 0); 01270 signal cfg_err_cor_n : std_logic; 01271 signal cfg_err_cpl_abort_n : std_logic; 01272 signal cfg_err_cpl_timeout_n : std_logic; 01273 signal cfg_err_cpl_unexpect_n : std_logic; 01274 signal cfg_err_ecrc_n : std_logic; 01275 signal cfg_err_locked_n : std_logic; 01276 signal cfg_err_posted_n : std_logic; 01277 signal cfg_err_ur_n : std_logic; 01278 signal cfg_interrupt_assert_n : std_logic; 01279 signal cfg_interrupt_n : std_logic; 01280 signal cfg_turnoff_ok_n : std_logic; 01281 signal cfg_turnoff_ok_axi : std_logic; 01282 signal cfg_pm_wake_n : std_logic; 01283 signal cfg_rd_en_n : std_logic; 01284 signal cfg_trn_pending_n : std_logic; 01285 signal cfg_wr_en_n : std_logic; 01286 signal tx_buf_av_int : std_logic_vector(5 downto 0); 01287 01288 signal pl_sel_link_rate_int : std_logic; 01289 signal pl_sel_link_width_int : std_logic_vector(1 downto 0); 01290 01291 signal LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus : std_logic; 01292 01293 begin 01294 -- Drive referenced outputs 01295 user_clk_out <= user_clk; 01296 user_reset_out <= user_reset_out_int; 01297 user_lnk_up <= user_lnk_up_int; 01298 pl_sel_link_rate <= pl_sel_link_rate_int; 01299 pl_sel_link_width <= pl_sel_link_width_int; 01300 tx_buf_av <= tx_buf_av_int; 01301 tx_cfg_req_int <= not(trn_tcfg_req_n); 01302 tx_cfg_req <= tx_cfg_req_int; 01303 cfg_pcie_link_state <= cfg_pcie_link_state_int; 01304 cfg_pmcsr_powerstate <= cfg_pmcsr_powerstate_int; 01305 cfg_to_turnoff_int <= cfg_msg_received_pme_to; 01306 cfg_to_turnoff <= cfg_to_turnoff_int; 01307 01308 -- Invert outputs 01309 tx_err_drop <= not(trn_terr_drop_n); 01310 cfg_rd_wr_done <= not(cfg_rd_wr_done_n); 01311 cfg_err_cpl_rdy <= not(cfg_err_cpl_rdy_n); 01312 cfg_interrupt_rdy <= not(cfg_interrupt_rdy_n); 01313 trn_tdst_rdy <= not(trn_tdst_rdy_n); 01314 trn_rsof <= not(trn_rsof_n); 01315 trn_reof <= not(trn_reof_n); 01316 trn_rrem(0) <= not(trn_rrem_n); 01317 trn_rsrc_rdy <= not(trn_rsrc_rdy_n); 01318 trn_rsrc_dsc <= not(trn_rsrc_dsc_n); 01319 trn_rerrfwd <= not(trn_rerrfwd_n); 01320 trn_rbar_hit <= not(trn_rbar_hit_n); 01321 trn_recrc_err <= not(trn_recrc_err_n); 01322 trn_rdllp_src_rdy <= not(trn_rdllp_src_rdy_n); 01323 01324 -- Invert inputs 01325 cfg_byte_en_n <= not(cfg_byte_en); 01326 cfg_err_cor_n <= not(cfg_err_cor); 01327 cfg_err_cpl_abort_n <= not(cfg_err_cpl_abort); 01328 cfg_err_cpl_timeout_n <= not(cfg_err_cpl_timeout); 01329 cfg_err_cpl_unexpect_n <= not(cfg_err_cpl_unexpect); 01330 cfg_err_ecrc_n <= not(cfg_err_ecrc); 01331 cfg_err_locked_n <= not(cfg_err_locked); 01332 cfg_err_posted_n <= not(cfg_err_posted); 01333 cfg_err_ur_n <= not(cfg_err_ur); 01334 cfg_interrupt_assert_n <= not(cfg_interrupt_assert); 01335 cfg_interrupt_n <= not(cfg_interrupt); 01336 cfg_turnoff_ok_n <= not(cfg_turnoff_ok_axi); 01337 cfg_pm_wake_n <= not(cfg_pm_wake); 01338 cfg_rd_en_n <= not(cfg_rd_en); 01339 cfg_trn_pending_n <= not(cfg_trn_pending); 01340 cfg_wr_en_n <= not(cfg_wr_en); 01341 trn_tcfg_gnt_n <= not(trn_tcfg_gnt); 01342 trn_rdst_rdy_n <= not(trn_rdst_rdy); 01343 trn_rnp_ok_n <= not(rx_np_ok); 01344 trn_tsof_n <= not(trn_tsof); 01345 trn_teof_n <= not(trn_teof); 01346 trn_tsrc_rdy_n <= not(trn_tsrc_rdy); 01347 trn_tsrc_dsc_n <= not(trn_tsrc_dsc); 01348 trn_terrfwd_n <= not(trn_terrfwd); 01349 trn_trem_n <= not(trn_trem(0)); 01350 trn_tstr_n <= not(trn_tstr); 01351 01352 LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus <= '1' when (LINK_STATUS_SLOT_CLOCK_CONFIG) else '0'; 01353 01354 -- Calculated/concatenated oututs 01355 cfg_status <= "0000000000000000"; 01356 cfg_command <= ("00000" & 01357 cfg_cmd_intdis & 01358 '0' & 01359 cfg_cmd_serr_en & 01360 "00000" & 01361 cfg_cmd_bme & 01362 cfg_cmd_mem_en & 01363 cfg_cmd_io_en); 01364 cfg_dstatus <= ("0000000000" & 01365 not(cfg_trn_pending_n) & 01366 '0' & 01367 cfg_dev_status_ur_detected & 01368 cfg_dev_status_fatal_err_detected & 01369 cfg_dev_status_nonfatal_err_detected & 01370 cfg_dev_status_corr_err_detected); 01371 cfg_dcommand <= ('0' & 01372 cfg_dev_control_max_read_req & 01373 cfg_dev_control_nosnoop_en & 01374 cfg_dev_control_aux_power_en & 01375 cfg_dev_control_phantom_en & 01376 cfg_dev_control_ext_tag_en & 01377 cfg_dev_control_maxpayload & 01378 cfg_dev_control_enable_relaxed_order & 01379 cfg_dev_control_ur_err_reporting_en & 01380 cfg_dev_control_fatal_err_reporting_en & 01381 cfg_dev_control_non_fatal_reporting_en & 01382 cfg_dev_control_corr_err_reporting_en); 01383 cfg_lstatus <= (cfg_link_status_autobandwidth_status & 01384 cfg_link_status_bandwidth_status & 01385 cfg_link_status_dll_active & 01386 LINK_STATUS_SLOT_CLOCK_CONFIG_lstatus & 01387 cfg_link_status_link_training & 01388 '0' & 01389 "00" & 01390 cfg_link_status_negotiated_link_width & 01391 "00" & 01392 cfg_link_status_current_speed); 01393 cfg_lcommand <= ("0000" & 01394 cfg_link_control_auto_bandwidth_int_en & 01395 cfg_link_control_bandwidth_int_en & 01396 cfg_link_control_hw_auto_width_dis & 01397 cfg_link_control_clock_pm_en & 01398 cfg_link_control_extended_sync & 01399 cfg_link_control_common_clock & 01400 cfg_link_control_retrain_link & 01401 cfg_link_control_linkdisable & 01402 cfg_link_control_rcb & 01403 '0' & 01404 cfg_link_control_aspm_control); 01405 cfg_bus_number <= cfg_bus_number_d; 01406 cfg_device_number <= cfg_device_number_d; 01407 cfg_function_number <= cfg_function_number_d; 01408 cfg_dcommand2 <= ("00000000000" & 01409 cfg_dev_control2_cpltimeout_dis & 01410 cfg_dev_control2_cpltimeout_val); 01411 01412 -- Capture Bus/Device/Function number 01413 01414 process (user_clk) 01415 begin 01416 if (rising_edge(user_clk)) then 01417 if (user_lnk_up_int = '0') then 01418 cfg_bus_number_d <= "00000000"; 01419 cfg_device_number_d <= "00000"; 01420 cfg_function_number_d <= "000"; 01421 elsif (cfg_msg_received = '0') then 01422 cfg_bus_number_d <= cfg_msg_data(15 downto 8); 01423 cfg_device_number_d <= cfg_msg_data(7 downto 3); 01424 cfg_function_number_d <= cfg_msg_data(2 downto 0); 01425 end if; 01426 end if; 01427 end process; 01428 01429 -- Generate user_lnk_up 01430 01431 user_lnk_up_int_i : FDCP 01432 generic map ( 01433 INIT => '0' 01434 ) 01435 port map ( 01436 Q => user_lnk_up_int, 01437 D => user_lnk_up_d, 01438 C => user_clk , 01439 CLR => '0' , 01440 PRE => '0' 01441 ); 01442 01443 user_lnk_up_d <= not(trn_lnk_up_n_1); 01444 01445 trn_lnk_up_n_1_i : FDCP 01446 generic map ( 01447 INIT => '1' 01448 ) 01449 port map ( 01450 Q => trn_lnk_up_n_1, 01451 D => trn_lnk_up_n, 01452 C => user_clk , 01453 CLR => '0' , 01454 PRE => '0' 01455 ); 01456 01457 01458 -- Generate user_reset_out 01459 01460 trn_reset_n_d <= not(trn_reset_n_int1 and not(phy_rdy_n)); 01461 sys_reset_d <= not(sys_reset_n_d); 01462 01463 trn_reset_n_i : FDCP 01464 generic map ( 01465 INIT => '1' 01466 ) 01467 port map ( 01468 Q => user_reset_out_int, 01469 D => trn_reset_n_d, 01470 C => user_clk , 01471 CLR => sys_reset_d , 01472 PRE => '0' 01473 ); 01474 01475 01476 trn_reset_n_1_d <= trn_reset_n and not(phy_rdy_n); 01477 trn_reset_n_int_i : FDCP 01478 generic map ( 01479 INIT => '0' 01480 ) 01481 port map ( 01482 Q => trn_reset_n_int1, 01483 D => trn_reset_n_1_d, 01484 C => user_clk , 01485 CLR => sys_reset_d , 01486 PRE => '0' 01487 ); 01488 01489 01490 --------------------------------------------------------- 01491 -- AXI Basic Bridge 01492 -- Converts between TRN and AXI 01493 --------------------------------------------------------- 01494 01495 axi_basic_top_i : axi_basic_top 01496 generic map ( 01497 C_DATA_WIDTH => 64, -- RX/TX interface data width 01498 C_REM_WIDTH => 1, -- trem/rrem width 01499 C_STRB_WIDTH => 8, -- tstrb width 01500 TCQ => 1, -- Clock to Q time 01501 01502 C_FAMILY => "V6", -- Targeted FPGA family 01503 C_ROOT_PORT => FALSE, -- PCIe block is in root port mode 01504 C_PM_PRIORITY => FALSE -- Disable TX packet boundary thrtl 01505 ) 01506 port map ( 01507 ------------------------------------------------- 01508 -- User Design I/O -- 01509 ------------------------------------------------- 01510 01511 -- AXI TX 01512 ------------- 01513 s_axis_tx_tdata => (others=>'0'), -- input 01514 s_axis_tx_tvalid => '0', -- input 01515 --s_axis_tx_tready => s_axis_tx_tready, -- output 01516 s_axis_tx_tstrb => (others=>'0'), -- input 01517 s_axis_tx_tlast => '0', -- input 01518 s_axis_tx_tuser => (others=>'0'), -- input 01519 01520 -- AXI RX 01521 ------------- 01522 --m_axis_rx_tdata => m_axis_rx_tdata, -- output 01523 --m_axis_rx_tvalid => m_axis_rx_tvalid, -- output 01524 m_axis_rx_tready => '0', -- input 01525 --m_axis_rx_tstrb => m_axis_rx_tstrb, -- output 01526 --m_axis_rx_tlast => m_axis_rx_tlast, -- output 01527 --m_axis_rx_tuser => m_axis_rx_tuser, -- output 01528 01529 -- User Misc. 01530 ------------- 01531 user_turnoff_ok => cfg_turnoff_ok, -- input 01532 user_tcfg_gnt => tx_cfg_gnt, -- input 01533 01534 ------------------------------------------------- 01535 -- PCIe Block I/O -- 01536 ------------------------------------------------- 01537 01538 -- TRN TX 01539 ------------- 01540 --trn_td => trn_td, -- output 01541 --trn_tsof => trn_tsof, -- output 01542 --trn_teof => trn_teof, -- output 01543 --trn_tsrc_rdy => trn_tsrc_rdy, -- output 01544 trn_tdst_rdy => '0', -- input 01545 --trn_tsrc_dsc => trn_tsrc_dsc, -- output 01546 --trn_trem => trn_trem, -- output 01547 --trn_terrfwd => trn_terrfwd, -- output 01548 --trn_tstr => trn_tstr, -- output 01549 trn_tbuf_av => tx_buf_av_int, -- input 01550 --trn_tecrc_gen => trn_tecrc_gen, -- output 01551 01552 -- TRN RX 01553 ------------- 01554 trn_rd => (others=>'0'), -- input 01555 trn_rsof => '1', -- input 01556 trn_reof => '1', -- input 01557 trn_rsrc_rdy => '1', -- input 01558 --trn_rdst_rdy => trn_rdst_rdy, -- output 01559 trn_rsrc_dsc => '1', -- input 01560 trn_rrem => "1", -- input 01561 trn_rerrfwd => '0', -- input 01562 trn_rbar_hit => (others=>'0'), -- input 01563 trn_recrc_err => '0', -- input 01564 01565 -- TRN Misc. 01566 ------------- 01567 trn_tcfg_req => tx_cfg_req_int, -- input 01568 trn_tcfg_gnt => trn_tcfg_gnt, -- output 01569 trn_lnk_up => user_lnk_up_int, -- input 01570 01571 -- Artix/Kintex/Virtex PM 01572 ------------- 01573 cfg_pcie_link_state => cfg_pcie_link_state_int, -- input 01574 01575 -- Virtex6 PM 01576 ------------- 01577 cfg_pm_send_pme_to => '0', -- input NOT USED FOR EP 01578 cfg_pmcsr_powerstate => cfg_pmcsr_powerstate_int, -- input 01579 trn_rdllp_data => trn_rdllp_data, -- input 01580 trn_rdllp_src_rdy => trn_rdllp_src_rdy, -- input 01581 01582 -- Power Mgmt for S6/V6 01583 ------------- 01584 cfg_to_turnoff => cfg_to_turnoff_int, -- input 01585 cfg_turnoff_ok => cfg_turnoff_ok_axi, -- output 01586 01587 -- System 01588 ------------- 01589 user_clk => user_clk, -- input 01590 user_rst => user_reset_out_int, -- input 01591 np_counter => open -- output 01592 ); 01593 01594 01595 01596 --cfg_turnoff_ok_axi <= '0'; 01597 --trn_tcfg_gnt <='0'; 01598 -- --------------------------------------------------------- 01599 -- PCI Express Reset Delay Module 01600 --------------------------------------------------------- 01601 01602 sys_reset_n <= not(sys_reset); 01603 01604 pcie_reset_delay_i : pcie_reset_delay_v6 01605 generic map ( 01606 PL_FAST_TRAIN => PL_FAST_TRAIN, 01607 REF_CLK_FREQ => REF_CLK_FREQ 01608 ) 01609 port map ( 01610 ref_clk => TxOutClk_bufg, 01611 sys_reset_n => sys_reset_n, 01612 delayed_sys_reset_n => sys_reset_n_d 01613 ); 01614 01615 01616 --------------------------------------------------------- 01617 -- PCI Express Clocking Module 01618 --------------------------------------------------------- 01619 01620 pcie_clocking_i : pcie_clocking_v6 01621 generic map ( 01622 CAP_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH_int , 01623 CAP_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int , 01624 REF_CLK_FREQ => REF_CLK_FREQ, 01625 USER_CLK_FREQ => USER_CLK_FREQ 01626 ) 01627 port map ( 01628 sys_clk => TxOutClk, 01629 gt_pll_lock => gt_pll_lock, 01630 sel_lnk_rate => pl_sel_link_rate_int, 01631 sel_lnk_width => pl_sel_link_width_int, 01632 sys_clk_bufg => TxOutClk_bufg, 01633 pipe_clk => pipe_clk, 01634 user_clk => user_clk, 01635 block_clk => open, 01636 drp_clk => drp_clk, 01637 clock_locked => clock_locked 01638 ); 01639 01640 01641 phy_rdy <= not(phy_rdy_n); 01642 01643 --------------------------------------------------------- 01644 -- Virtex6 PCI Express Block Module 01645 --------------------------------------------------------- 01646 01647 pcie_2_0_i : pcie_2_0_v6 01648 generic map ( 01649 REF_CLK_FREQ => REF_CLK_FREQ, 01650 PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES, 01651 LINK_CAP_MAX_LINK_WIDTH_int => LINK_CAP_MAX_LINK_WIDTH_int, 01652 AER_BASE_PTR => AER_BASE_PTR, 01653 AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE, 01654 AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE, 01655 AER_CAP_ID => AER_CAP_ID, 01656 AER_CAP_INT_MSG_NUM_MSI => AER_CAP_INT_MSG_NUM_MSI, 01657 AER_CAP_INT_MSG_NUM_MSIX => AER_CAP_INT_MSG_NUM_MSIX, 01658 AER_CAP_NEXTPTR => AER_CAP_NEXTPTR, 01659 AER_CAP_ON => AER_CAP_ON, 01660 AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE, 01661 AER_CAP_VERSION => AER_CAP_VERSION, 01662 ALLOW_X8_GEN2 => ALLOW_X8_GEN2, 01663 BAR0 => pad_gen(BAR0, 32), 01664 BAR1 => pad_gen(BAR1, 32), 01665 BAR2 => pad_gen(BAR2, 32), 01666 BAR3 => pad_gen(BAR3, 32), 01667 BAR4 => pad_gen(BAR4, 32), 01668 BAR5 => pad_gen(BAR5, 32), 01669 CAPABILITIES_PTR => CAPABILITIES_PTR, 01670 CARDBUS_CIS_POINTER => pad_gen(CARDBUS_CIS_POINTER, 32), 01671 CLASS_CODE => pad_gen(CLASS_CODE, 24), 01672 CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED, 01673 CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED, 01674 CPL_TIMEOUT_RANGES_SUPPORTED => pad_gen(CPL_TIMEOUT_RANGES_SUPPORTED, 4), 01675 CRM_MODULE_RSTS => CRM_MODULE_RSTS, 01676 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE, 01677 DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE, 01678 DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY, 01679 DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY, 01680 DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED, 01681 DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE, 01682 DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED, 01683 DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT, 01684 DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR, 01685 DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12, 01686 DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16, 01687 DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29, 01688 DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED, 01689 DEVICE_ID => pad_gen(DEVICE_ID, 16), 01690 DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER, 01691 DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING, 01692 DISABLE_ID_CHECK => DISABLE_ID_CHECK, 01693 DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL, 01694 DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER, 01695 DISABLE_SCRAMBLING => DISABLE_SCRAMBLING, 01696 DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM, 01697 DSN_BASE_PTR => pad_gen(DSN_BASE_PTR, 12), 01698 DSN_CAP_ID => DSN_CAP_ID, 01699 DSN_CAP_NEXTPTR => pad_gen(DSN_CAP_NEXTPTR, 12), 01700 DSN_CAP_ON => DSN_CAP_ON, 01701 DSN_CAP_VERSION => DSN_CAP_VERSION, 01702 ENABLE_MSG_ROUTE => pad_gen(ENABLE_MSG_ROUTE, 11), 01703 ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM, 01704 ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0, 01705 EXPANSION_ROM => pad_gen(EXPANSION_ROM, 32), 01706 EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR, 01707 EXT_CFG_XP_CAP_PTR => pad_gen(EXT_CFG_XP_CAP_PTR, 10), 01708 HEADER_TYPE => pad_gen(HEADER_TYPE, 8), 01709 INFER_EI => INFER_EI, 01710 INTERRUPT_PIN => pad_gen(INTERRUPT_PIN, 8), 01711 IS_SWITCH => IS_SWITCH, 01712 LAST_CONFIG_DWORD => LAST_CONFIG_DWORD, 01713 LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT, 01714 LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT, 01715 LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP, 01716 LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP, 01717 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1, 01718 LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2, 01719 LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1, 01720 LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2, 01721 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1, 01722 LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2, 01723 LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1, 01724 LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2, 01725 LINK_CAP_MAX_LINK_SPEED => pad_gen(LINK_CAP_MAX_LINK_SPEED, 4), 01726 LINK_CAP_MAX_LINK_WIDTH => pad_gen(LINK_CAP_MAX_LINK_WIDTH, 6), 01727 LINK_CAP_RSVD_23_22 => LINK_CAP_RSVD_23_22, 01728 LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE, 01729 LINK_CONTROL_RCB => LINK_CONTROL_RCB, 01730 LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS, 01731 LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE, 01732 LINK_CTRL2_TARGET_LINK_SPEED => pad_gen(LINK_CTRL2_TARGET_LINK_SPEED, 4), 01733 LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG, 01734 LL_ACK_TIMEOUT => pad_gen(LL_ACK_TIMEOUT, 15), 01735 LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN, 01736 LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC, 01737 LL_REPLAY_TIMEOUT => pad_gen(LL_REPLAY_TIMEOUT, 15), 01738 LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN, 01739 LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC, 01740 LTSSM_MAX_LINK_WIDTH => pad_gen(LTSSM_MAX_LINK_WIDTH, 6), 01741 MSI_BASE_PTR => MSI_BASE_PTR, 01742 MSI_CAP_ID => MSI_CAP_ID, 01743 MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP, 01744 MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION, 01745 MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR, 01746 MSI_CAP_ON => MSI_CAP_ON, 01747 MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE, 01748 MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE, 01749 MSIX_BASE_PTR => MSIX_BASE_PTR, 01750 MSIX_CAP_ID => MSIX_CAP_ID, 01751 MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR, 01752 MSIX_CAP_ON => MSIX_CAP_ON, 01753 MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR, 01754 MSIX_CAP_PBA_OFFSET => pad_gen(MSIX_CAP_PBA_OFFSET, 29), 01755 MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR, 01756 MSIX_CAP_TABLE_OFFSET => pad_gen(MSIX_CAP_TABLE_OFFSET, 29), 01757 MSIX_CAP_TABLE_SIZE => pad_gen(MSIX_CAP_TABLE_SIZE, 11), 01758 N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1, 01759 N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2, 01760 N_FTS_GEN1 => N_FTS_GEN1, 01761 N_FTS_GEN2 => N_FTS_GEN2, 01762 PCIE_BASE_PTR => PCIE_BASE_PTR, 01763 PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID, 01764 PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION, 01765 PCIE_CAP_DEVICE_PORT_TYPE => pad_gen(PCIE_CAP_DEVICE_PORT_TYPE, 4), 01766 PCIE_CAP_INT_MSG_NUM => pad_gen(PCIE_CAP_INT_MSG_NUM, 5), 01767 PCIE_CAP_NEXTPTR => pad_gen(PCIE_CAP_NEXTPTR, 8), 01768 PCIE_CAP_ON => PCIE_CAP_ON, 01769 PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14, 01770 PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED, 01771 PCIE_REVISION => PCIE_REVISION, 01772 PGL0_LANE => PGL0_LANE, 01773 PGL1_LANE => PGL1_LANE, 01774 PGL2_LANE => PGL2_LANE, 01775 PGL3_LANE => PGL3_LANE, 01776 PGL4_LANE => PGL4_LANE, 01777 PGL5_LANE => PGL5_LANE, 01778 PGL6_LANE => PGL6_LANE, 01779 PGL7_LANE => PGL7_LANE, 01780 PL_AUTO_CONFIG => PL_AUTO_CONFIG, 01781 PL_FAST_TRAIN => PL_FAST_TRAIN, 01782 PM_BASE_PTR => PM_BASE_PTR, 01783 PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT, 01784 PM_CAP_DSI => PM_CAP_DSI, 01785 PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT, 01786 PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT, 01787 PM_CAP_ID => PM_CAP_ID, 01788 PM_CAP_NEXTPTR => PM_CAP_NEXTPTR, 01789 PM_CAP_ON => PM_CAP_ON, 01790 PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK, 01791 PM_CAP_PMESUPPORT => pad_gen(PM_CAP_PMESUPPORT, 5), 01792 PM_CAP_RSVD_04 => PM_CAP_RSVD_04, 01793 PM_CAP_VERSION => PM_CAP_VERSION, 01794 PM_CSR_BPCCEN => PM_CSR_BPCCEN, 01795 PM_CSR_B2B3 => PM_CSR_B2B3, 01796 PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST, 01797 PM_DATA_SCALE0 => pad_gen(PM_DATA_SCALE0, 2), 01798 PM_DATA_SCALE1 => pad_gen(PM_DATA_SCALE1, 2), 01799 PM_DATA_SCALE2 => pad_gen(PM_DATA_SCALE2, 2), 01800 PM_DATA_SCALE3 => pad_gen(PM_DATA_SCALE3, 2), 01801 PM_DATA_SCALE4 => pad_gen(PM_DATA_SCALE4, 2), 01802 PM_DATA_SCALE5 => pad_gen(PM_DATA_SCALE5, 2), 01803 PM_DATA_SCALE6 => pad_gen(PM_DATA_SCALE6, 2), 01804 PM_DATA_SCALE7 => pad_gen(PM_DATA_SCALE7, 2), 01805 PM_DATA0 => pad_gen(PM_DATA0, 8), 01806 PM_DATA1 => pad_gen(PM_DATA1, 8), 01807 PM_DATA2 => pad_gen(PM_DATA2, 8), 01808 PM_DATA3 => pad_gen(PM_DATA3, 8), 01809 PM_DATA4 => pad_gen(PM_DATA4, 8), 01810 PM_DATA5 => pad_gen(PM_DATA5, 8), 01811 PM_DATA6 => pad_gen(PM_DATA6, 8), 01812 PM_DATA7 => pad_gen(PM_DATA7, 8), 01813 RECRC_CHK => RECRC_CHK, 01814 RECRC_CHK_TRIM => RECRC_CHK_TRIM, 01815 REVISION_ID => pad_gen(REVISION_ID, 8), 01816 ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY, 01817 SELECT_DLL_IF => SELECT_DLL_IF, 01818 SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT, 01819 SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT, 01820 SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT, 01821 SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE, 01822 SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE, 01823 SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT, 01824 SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT, 01825 SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM, 01826 SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT, 01827 SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT, 01828 SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE, 01829 SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE, 01830 SPARE_BIT0 => SPARE_BIT0, 01831 SPARE_BIT1 => SPARE_BIT1, 01832 SPARE_BIT2 => SPARE_BIT2, 01833 SPARE_BIT3 => SPARE_BIT3, 01834 SPARE_BIT4 => SPARE_BIT4, 01835 SPARE_BIT5 => SPARE_BIT5, 01836 SPARE_BIT6 => SPARE_BIT6, 01837 SPARE_BIT7 => SPARE_BIT7, 01838 SPARE_BIT8 => SPARE_BIT8, 01839 SPARE_BYTE0 => SPARE_BYTE0, 01840 SPARE_BYTE1 => SPARE_BYTE1, 01841 SPARE_BYTE2 => SPARE_BYTE2, 01842 SPARE_BYTE3 => SPARE_BYTE3, 01843 SPARE_WORD0 => SPARE_WORD0, 01844 SPARE_WORD1 => SPARE_WORD1, 01845 SPARE_WORD2 => SPARE_WORD2, 01846 SPARE_WORD3 => SPARE_WORD3, 01847 SUBSYSTEM_ID => pad_gen(SUBSYSTEM_ID, 16), 01848 SUBSYSTEM_VENDOR_ID => pad_gen(SUBSYSTEM_VENDOR_ID, 16), 01849 TL_RBYPASS => TL_RBYPASS, 01850 TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY, 01851 TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY, 01852 TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY, 01853 TL_TFC_DISABLE => TL_TFC_DISABLE, 01854 TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE, 01855 TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY, 01856 TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY, 01857 TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY, 01858 UPCONFIG_CAPABLE => UPCONFIG_CAPABLE, 01859 UPSTREAM_FACING => UPSTREAM_FACING, 01860 EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI, 01861 UR_INV_REQ => UR_INV_REQ, 01862 USER_CLK_FREQ => USER_CLK_FREQ, 01863 VC_BASE_PTR => pad_gen(VC_BASE_PTR, 12), 01864 VC_CAP_ID => VC_CAP_ID, 01865 VC_CAP_NEXTPTR => pad_gen(VC_CAP_NEXTPTR, 12), 01866 VC_CAP_ON => VC_CAP_ON, 01867 VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS, 01868 VC_CAP_VERSION => VC_CAP_VERSION, 01869 VC0_CPL_INFINITE => VC0_CPL_INFINITE, 01870 VC0_RX_RAM_LIMIT => pad_gen(VC0_RX_RAM_LIMIT, 13), 01871 VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD, 01872 VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH, 01873 VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH, 01874 VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD, 01875 VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH, 01876 VC0_TX_LASTPACKET => VC0_TX_LASTPACKET, 01877 VENDOR_ID => pad_gen(VENDOR_ID, 16), 01878 VSEC_BASE_PTR => pad_gen(VSEC_BASE_PTR, 12), 01879 VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID, 01880 VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH, 01881 VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION, 01882 VSEC_CAP_ID => VSEC_CAP_ID, 01883 VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE, 01884 VSEC_CAP_NEXTPTR => pad_gen(VSEC_CAP_NEXTPTR, 12), 01885 VSEC_CAP_ON => VSEC_CAP_ON, 01886 VSEC_CAP_VERSION => VSEC_CAP_VERSION 01887 ) 01888 port map ( 01889 PCIEXPRXN => pci_exp_rxn, 01890 PCIEXPRXP => pci_exp_rxp, 01891 PCIEXPTXN => pci_exp_txn, 01892 PCIEXPTXP => pci_exp_txp, 01893 SYSCLK => sys_clk, 01894 TRNLNKUPN => trn_lnk_up_n, 01895 FUNDRSTN => sys_reset_n_d, 01896 PHYRDYN => phy_rdy_n, 01897 LNKCLKEN => open, 01898 USERRSTN => trn_reset_n, 01899 RECEIVEDFUNCLVLRSTN => rx_func_level_reset_n, 01900 SYSRSTN => phy_rdy, 01901 PLRSTN => '1', 01902 DLRSTN => '1', 01903 TLRSTN => '1', 01904 FUNCLVLRSTN => '1', 01905 CMRSTN => '1', 01906 CMSTICKYRSTN => '1', 01907 01908 TRNRBARHITN => trn_rbar_hit_n, 01909 TRNRD => trn_rd, 01910 TRNRECRCERRN => trn_recrc_err_n, 01911 TRNREOFN => trn_reof_n, 01912 TRNRERRFWDN => trn_rerrfwd_n, 01913 TRNRREMN => trn_rrem_n, 01914 TRNRSOFN => trn_rsof_n, 01915 TRNRSRCDSCN => trn_rsrc_dsc_n, 01916 TRNRSRCRDYN => trn_rsrc_rdy_n, 01917 TRNRDSTRDYN => trn_rdst_rdy_n, 01918 TRNRNPOKN => trn_rnp_ok_n, 01919 TRNRDLLPDATA => trn_rdllp_data, 01920 TRNRDLLPSRCRDYN => trn_rdllp_src_rdy_n, 01921 01922 TRNTBUFAV => tx_buf_av_int, 01923 TRNTCFGREQN => trn_tcfg_req_n, 01924 TRNTDLLPDSTRDYN => open, 01925 TRNTDSTRDYN => trn_tdst_rdy_n, 01926 TRNTERRDROPN => trn_terr_drop_n, 01927 TRNTCFGGNTN => trn_tcfg_gnt_n, 01928 TRNTD => trn_td, 01929 TRNTDLLPDATA => (others => '0'), 01930 TRNTDLLPSRCRDYN => '1', 01931 TRNTECRCGENN => '1', 01932 TRNTEOFN => trn_teof_n, 01933 TRNTERRFWDN => trn_terrfwd_n, 01934 TRNTREMN => trn_trem_n, 01935 TRNTSOFN => trn_tsof_n, 01936 TRNTSRCDSCN => trn_tsrc_dsc_n, 01937 TRNTSRCRDYN => trn_tsrc_rdy_n, 01938 TRNTSTRN => trn_tstr_n, 01939 TRNFCCPLD => fc_cpld, 01940 TRNFCCPLH => fc_cplh, 01941 TRNFCNPD => fc_npd, 01942 TRNFCNPH => fc_nph, 01943 TRNFCPD => fc_pd, 01944 TRNFCPH => fc_ph, 01945 TRNFCSEL => fc_sel, 01946 CFGAERECRCCHECKEN => open, 01947 CFGAERECRCGENEN => open, 01948 CFGCOMMANDBUSMASTERENABLE => cfg_cmd_bme, 01949 CFGCOMMANDINTERRUPTDISABLE => cfg_cmd_intdis, 01950 CFGCOMMANDIOENABLE => cfg_cmd_io_en, 01951 CFGCOMMANDMEMENABLE => cfg_cmd_mem_en, 01952 CFGCOMMANDSERREN => cfg_cmd_serr_en, 01953 CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en, 01954 CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en, 01955 CFGDEVCONTROLENABLERO => cfg_dev_control_enable_relaxed_order, 01956 CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en, 01957 CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en, 01958 CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_maxpayload, 01959 CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req, 01960 CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en, 01961 CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_nosnoop_en, 01962 CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en, 01963 CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en, 01964 CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dev_control2_cpltimeout_dis, 01965 CFGDEVCONTROL2CPLTIMEOUTVAL => cfg_dev_control2_cpltimeout_val, 01966 CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected, 01967 CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected, 01968 CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_nonfatal_err_detected, 01969 CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected, 01970 CFGDO => cfg_do, 01971 CFGERRAERHEADERLOGSETN => open , 01972 CFGERRCPLRDYN => cfg_err_cpl_rdy_n, 01973 CFGINTERRUPTDO => cfg_interrupt_do, 01974 CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable, 01975 CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable, 01976 CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable, 01977 CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm, 01978 CFGINTERRUPTRDYN => cfg_interrupt_rdy_n, 01979 CFGLINKCONTROLRCB => cfg_link_control_rcb, 01980 CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control, 01981 CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_link_control_auto_bandwidth_int_en, 01982 CFGLINKCONTROLBANDWIDTHINTEN => cfg_link_control_bandwidth_int_en, 01983 CFGLINKCONTROLCLOCKPMEN => cfg_link_control_clock_pm_en, 01984 CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock, 01985 CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync, 01986 CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_link_control_hw_auto_width_dis, 01987 CFGLINKCONTROLLINKDISABLE => cfg_link_control_linkdisable, 01988 CFGLINKCONTROLRETRAINLINK => cfg_link_control_retrain_link, 01989 CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_link_status_autobandwidth_status, 01990 CFGLINKSTATUSBANDWITHSTATUS => cfg_link_status_bandwidth_status, 01991 CFGLINKSTATUSCURRENTSPEED => cfg_link_status_current_speed, 01992 CFGLINKSTATUSDLLACTIVE => cfg_link_status_dll_active, 01993 CFGLINKSTATUSLINKTRAINING => cfg_link_status_link_training, 01994 CFGLINKSTATUSNEGOTIATEDWIDTH => cfg_link_status_negotiated_link_width, 01995 CFGMSGDATA => cfg_msg_data, 01996 CFGMSGRECEIVED => cfg_msg_received, 01997 CFGMSGRECEIVEDASSERTINTA => open, 01998 CFGMSGRECEIVEDASSERTINTB => open, 01999 CFGMSGRECEIVEDASSERTINTC => open, 02000 CFGMSGRECEIVEDASSERTINTD => open, 02001 CFGMSGRECEIVEDDEASSERTINTA => open, 02002 CFGMSGRECEIVEDDEASSERTINTB => open, 02003 CFGMSGRECEIVEDDEASSERTINTC => open, 02004 CFGMSGRECEIVEDDEASSERTINTD => open, 02005 CFGMSGRECEIVEDERRCOR => open, 02006 CFGMSGRECEIVEDERRFATAL => open, 02007 CFGMSGRECEIVEDERRNONFATAL => open, 02008 CFGMSGRECEIVEDPMASNAK => open, 02009 CFGMSGRECEIVEDPMETO => cfg_msg_received_pme_to, 02010 CFGMSGRECEIVEDPMETOACK => open, 02011 CFGMSGRECEIVEDPMPME => open, 02012 CFGMSGRECEIVEDSETSLOTPOWERLIMIT => open, 02013 CFGMSGRECEIVEDUNLOCK => open, 02014 CFGPCIELINKSTATE => cfg_pcie_link_state_int, 02015 CFGPMCSRPMEEN => cfg_pmcsr_pme_en, 02016 CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status, 02017 CFGPMCSRPOWERSTATE => cfg_pmcsr_powerstate_int, 02018 CFGPMRCVASREQL1N => open, 02019 CFGPMRCVENTERL1N => open, 02020 CFGPMRCVENTERL23N => open, 02021 CFGPMRCVREQACKN => open, 02022 CFGRDWRDONEN => cfg_rd_wr_done_n, 02023 CFGSLOTCONTROLELECTROMECHILCTLPULSE => open, 02024 CFGTRANSACTION => open, 02025 CFGTRANSACTIONADDR => open, 02026 CFGTRANSACTIONTYPE => open, 02027 CFGVCTCVCMAP => open, 02028 CFGBYTEENN => cfg_byte_en_n, 02029 CFGDI => cfg_di, 02030 CFGDSBUSNUMBER => "00000000", 02031 CFGDSDEVICENUMBER => "00000", 02032 CFGDSFUNCTIONNUMBER => "000", 02033 CFGDSN => cfg_dsn, 02034 CFGDWADDR => cfg_dwaddr, 02035 CFGERRACSN => '1', 02036 CFGERRAERHEADERLOG => (others => '0'), 02037 CFGERRCORN => cfg_err_cor_n, 02038 CFGERRCPLABORTN => cfg_err_cpl_abort_n, 02039 CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n, 02040 CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n, 02041 CFGERRECRCN => cfg_err_ecrc_n, 02042 CFGERRLOCKEDN => cfg_err_locked_n, 02043 CFGERRPOSTEDN => cfg_err_posted_n, 02044 CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header, 02045 CFGERRURN => cfg_err_ur_n, 02046 CFGINTERRUPTASSERTN => cfg_interrupt_assert_n, 02047 CFGINTERRUPTDI => cfg_interrupt_di, 02048 CFGINTERRUPTN => cfg_interrupt_n, 02049 CFGPMDIRECTASPML1N => '1', 02050 CFGPMSENDPMACKN => '1', 02051 CFGPMSENDPMETON => '1', 02052 CFGPMSENDPMNAKN => '1', 02053 CFGPMTURNOFFOKN => cfg_turnoff_ok_n, 02054 CFGPMWAKEN => cfg_pm_wake_n, 02055 CFGPORTNUMBER => "00000000", 02056 CFGRDENN => cfg_rd_en_n, 02057 CFGTRNPENDINGN => cfg_trn_pending_n, 02058 CFGWRENN => cfg_wr_en_n, 02059 CFGWRREADONLYN => '1', 02060 CFGWRRW1CASRWN => '1', 02061 02062 PLINITIALLINKWIDTH => pl_initial_link_width, 02063 PLLANEREVERSALMODE => pl_lane_reversal_mode, 02064 PLLINKGEN2CAP => pl_link_gen2_capable, 02065 PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported, 02066 PLLINKUPCFGCAP => pl_link_upcfg_capable, 02067 PLLTSSMSTATE => pl_ltssm_state, 02068 PLPHYLNKUPN => open, -- Debug 02069 PLRECEIVEDHOTRST => pl_received_hot_rst, 02070 PLRXPMSTATE => open, -- Debug 02071 PLSELLNKRATE => pl_sel_link_rate_int, 02072 PLSELLNKWIDTH => pl_sel_link_width_int, 02073 PLTXPMSTATE => open, -- Debug 02074 PLDIRECTEDLINKAUTON => pl_directed_link_auton, 02075 PLDIRECTEDLINKCHANGE => pl_directed_link_change, 02076 PLDIRECTEDLINKSPEED => pl_directed_link_speed, 02077 PLDIRECTEDLINKWIDTH => pl_directed_link_width, 02078 PLDOWNSTREAMDEEMPHSOURCE => '1', 02079 PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph, 02080 PLTRANSMITHOTRST => '0', 02081 02082 DBGSCLRA => open, 02083 DBGSCLRB => open, 02084 DBGSCLRC => open, 02085 DBGSCLRD => open, 02086 DBGSCLRE => open, 02087 DBGSCLRF => open, 02088 DBGSCLRG => open, 02089 DBGSCLRH => open, 02090 DBGSCLRI => open, 02091 DBGSCLRJ => open, 02092 DBGSCLRK => open, 02093 DBGVECA => open, 02094 DBGVECB => open, 02095 DBGVECC => open, 02096 PLDBGVEC => open, 02097 DBGMODE => "00", 02098 DBGSUBMODE => '0', 02099 PLDBGMODE => "000", 02100 02101 PCIEDRPDO => open, 02102 PCIEDRPDRDY => open, 02103 PCIEDRPCLK => '0', 02104 PCIEDRPDADDR => "000000000" , 02105 PCIEDRPDEN => '0', 02106 PCIEDRPDI => X"0000", 02107 PCIEDRPDWE => '0', 02108 02109 GTPLLLOCK => gt_pll_lock , 02110 PIPECLK => pipe_clk, 02111 USERCLK => user_clk, 02112 DRPCLK => drp_clk, 02113 CLOCKLOCKED => clock_locked , 02114 TxOutClk => TxOutClk 02115 ); 02116 02117 end v6_pcie; 02118
1.7.4