Граф наследования:ambpex5_v20_sx50t_core:
Constants | |
| rom_main | bl_trd_rom := ( 0 = >ID_MAIN , 1 = >ID_MODE_MAIN , 2 = >VER_MAIN , 3 = >RES_MAIN , 4 = >FIFO_MAIN , 5 = >FTYPE_MAIN , 6 = >x " 0100 " , 7 = >x " 0001 " , 8 = >x " 4953 " , 9 = >x " 0200 " , 10 = >x " 0100 " , 11 = >x " 0000 " , 12 = > " 0000000011001011 " , 13 = >x " 0000 " , 14 = >x " 0000 " , 15 = >x " 0000 " , 16 = >x " 5507 " , 17 = >x " 0200 " , 18 = >x " 0000 " , 19 = >x " 0000 " , 20 = >x " 0109 " , 31 downto 21 = > x " 0000 " ) |
| rom_dio_in | bl_trd_rom := ( 0 = >ID_DIO_IN , 1 = >ID_MODE_DIO_IN , 2 = >VER_DIO_IN , 3 = >RES_DIO_IN , 4 = >FIFO_DIO_IN , 5 = >FTYPE_DIO_IN , 6 = >x " 010D " , 7 = >x " 0001 " , 31 downto 8 = > x " 0000 " ) |
| rom_dio_out | bl_trd_rom := ( 0 = >ID_DIO_OUT , 1 = >ID_MODE_DIO_OUT , 2 = >VER_DIO_OUT , 3 = >RES_DIO_OUT , 4 = >FIFO_DIO_OUT , 5 = >FTYPE_DIO_OUT , 6 = >x " 0C01 " , 7 = >x " 0001 " , 31 downto 8 = > x " 0000 " ) |
| rom_test_ctrl | bl_trd_rom := ( 0 = >ID_TEST , 1 = >ID_MODE_TEST , 2 = >VER_TEST , 3 = >RES_TEST , 4 = >FIFO_TEST , 5 = >FTYPE_TEST , 6 = >x " 0000 " , 7 = >x " 0001 " , 31 downto 8 = > x " 0000 " ) |
| trd_rom | std_logic_array_16xbl_trd_rom := ( 0 = > rom_main , 1 = > rom_test_ctrl , 2 = > rom_empty , 3 = > rom_empty , 4 = > rom_empty , 5 = > rom_empty , 6 = > rom_dio_in , 7 = > rom_dio_out , others = > rom_empty ) |
Signals | |
| clk | std_logic |
| reset_main | std_logic |
| reset | std_logic |
| trd_host_adr | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
| trd_host_data | std_logic_array_16x64 |
| trd_host_cmd_data | std_logic_array_16x16 |
| trd_host_cmd | std_logic_array_16xbl_cmd |
| trd_data | std_logic_array_16x64 := ( others = > ( others = > ' 0 ' ) ) |
| trd_cmd_data | std_logic_array_16x16 := ( others = > ( others = > ' 1 ' ) ) |
| trd_drq | std_logic_array_16xbl_drq := ( others = > ( others = > ' 0 ' ) ) |
| trd_irq | std_logic_array_16xbl_irq := ( others = > ' 0 ' ) |
| trd_reset_fifo | std_logic_array_16xbl_reset_fifo := ( others = > ' 0 ' ) |
| trd_main_drq | std_logic_array_16xbl_drq := ( others = > ( others = > ' 0 ' ) ) |
| trd_main_irq | std_logic_array_16xbl_irq := ( others = > ' 0 ' ) |
| trd_main_sel_drq | std_logic_array_16x6 := ( others = > ( others = > ' 0 ' ) ) |
| test_mode | std_logic |
| trd_trd_cmd | std_logic_array_16xbl_cmd |
| trd_flag_rd | std_logic_array_16xbl_fifo_flag |
| di_mode1 | std_logic_vector ( 15 downto 0 ) |
| di_data | std_logic_vector ( 63 downto 0 ) |
| di_data_we | std_logic |
| di_flag_wr | bl_fifo_flag |
| di_start | std_logic |
| di_fifo_rst | std_logic |
| di_clk | std_logic |
| do_mode1 | std_logic_vector ( 15 downto 0 ) |
| do_data | std_logic_vector ( 63 downto 0 ) |
| do_data_cs | std_logic |
| do_flag_rd | bl_fifo_flag |
| do_start | std_logic |
| do_fifo_rst | std_logic |
| do_clk | std_logic |
| clk200 | std_logic |
| freq0 | std_logic |
| freq1 | std_logic |
| freq2 | std_logic |
| led_h1 | std_logic |
| led_h2 | std_logic |
| led_h3 | std_logic |
| led_h4 | std_logic |
| tp1 | std_logic |
| tp2 | std_logic |
| tp3 | std_logic |
| px | std_logic_vector ( 3 downto 1 ) |
| clk30k | std_logic |
Component Instantiations | |
| xled1 | obuf_s_16 |
| xled2 | obuf_s_16 |
| xled3 | obuf_s_16 |
| xled4 | obuf_s_16 |
| btp1 | obuf_f_16 |
| btp2 | obuf_f_16 |
| btp3 | obuf_f_16 |
| amb | cl_ambpex5_m5 <Entity cl_ambpex5_m5> |
| main | trd_main_v8 <Entity trd_main_v8> |
| dio_in | trd_admdio64_in_v6 <Entity trd_admdio64_in_v6> |
| dio_out | trd_admdio64_out_v4 <Entity trd_admdio64_out_v4> |
| test_ctrl | trd_test_ctrl_m1 <Entity trd_test_ctrl_m1> |
Подробное описание
См. определение в файле ambpex5_v20_sx50t_core.vhd строка 98
Объявления и описания членов класса находятся в файле:
